Electrical Testing TRIZ Cases

Bit clustering system identifies and classifies random and systematic bitmap failures using configurable radius parameters.

A diagnostic abort control circuit gradually reduces test clock frequency during self-diagnosis termination.

A device detects faults by comparing the current signal frequency to a natural frequency threshold.

Diagnostic method measures high-frequency impedance to estimate theoretical voltage and detect faults in fuel cells.

A bus bar module uses a bent tongue piece to reduce projection dimensions while maintaining winding efficiency.

Interface control circuit isolates adjoining memory cells via bank selection, enabling marching tests without exclusive-use patterns or additional hardware.

A method estimates battery state-of-health using relaxing voltage fingerprints measured during rest periods.

A prediction module selects machine learning models from an ensemble to forecast future battery state-of-health values using historical data inputs.

Machine learning correction models compensate for physical model errors to improve state of health prediction accuracy.

A diagnostic procedure measures electrochemical energy storage voltage gradients during controlled discharge cycles to determine device health.

A distance protection relay determines line and earth admittances from sampled signals.

An automated framework creates test instances via constraint satisfaction to eliminate manual coding effort in electronic design verification.

Compact test instrument with embedded computer and web service interface for autonomous JTAG sequence execution.

A battery fuel gauge circuit estimates state of charge using coulomb counting and electromotive force detection.

Pre-positioned switching elements enable realistic short circuit simulation without structural modifications, improving test validity.

Comparing group resistance against a reference value detects heater faults, preventing gas condensation hazards.

Vertical stacking of motherboards increases testing throughput without expanding robotic arm reach or cost.

An estimation device approximates capacity change curves using multiple straight lines to calculate actual battery capacity.

A method estimates physico-chemical parameters using combined sinusoidal and step electrical excitations to determine device health.

A battery formation testing controller determines the transfer function of a current sensor to correct gain and offset variations.

A trimmable on-chip oscillator generates precise launch and capture pulses for at-speed delay fault testing.

A battery monitoring device uses dynamic amplification to calculate internal resistance values from differential voltage signals.

Movable guide plates in a probe storage jig expose critical probe areas, enabling defect detection before circuit assembly.

Equivalent RC circuit models processed by weighted recursive least squares algorithms improve measurement precision for battery state estimation.

A battery management system estimates state-of-health using internal resistance and temperature measurements applied to a pre-established cartography.

Multiplexers share analog-to-digital converters across battery cells, reducing integrated circuit count while maintaining measurement precision.

A battery management system adjusts capacity estimates using dynamic weighting factors based on measurement quality.

Test switches isolate intermediate nodes to enable accurate transistor characterization within integrated circuit memory sections.

Partial charge cycles correct cumulative estimation errors without full discharges, extending battery life.

A health sense circuit measures current through a magnetic coil to determine its operational status.

A condition monitoring unit measures circuit currents and voltages to determine dynamic threshold values for event detection.

A semiconductor apparatus uses a data alignment circuit to align input data across multiple pads, generating precise write patterns for testing.

A battery monitoring system displays cell data in polar coordinate graphical images for simultaneous multi-string viewing.

A MEMS sensor diagnostic system rewrites response coefficients and generates test output signals for verification.

A self-calibrating cell voltage monitoring device adjusts measurements using internal compensation values.

A model checker generates deep traces from an integrated circuit under test to evaluate user logic assertions directly on the chip.

A reduced-order electrochemical battery model updates effective diffusion and resistance parameters to estimate state variables.

A TCAM macro cell configuration reduces test signal wirings through match line selection circuits and scan input mechanisms.

A unified probe assembly detects electric and magnetic fields simultaneously on a single circuit board.

A fuel gauge measures open circuit voltage before device operation to determine battery state of charge.

A computer-implemented method segments battery voltage and current data into subsets to determine state of health over time.

Convolutional neural networks process multi-frequency impedance spectra to enhance estimation accuracy while managing processing complexity.

A battery monitoring system calculates remaining energy using sensor inputs and a touch screen interface for user interaction.

A hydraulic stage adjusts probe positions within a sealed chamber without opening the enclosure.

Adaptive gain control engine adjusts battery state of charge estimation using current and voltage data to resolve accuracy errors during dynamic load changes.

A computing device extracts data flow paths from SCD files to calculate logical node reliability measures for substation automation systems.

A hybrid lithium-ion battery model switches between static and dynamic equivalent circuits to estimate load current.

A secondary battery state estimating device calculates internal states using a model equation with diffusion coefficients and DC resistance parameters.

A multi-layered plunger assembly with an interposer substrate transmits millimeter wave signals through a test kit.

A semiconductor memory apparatus uses a delay control unit to generate staggered test signals, resolving limited pin constraints during multi-die testing.