Semiconductor Memory Stacked Die Test Control
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Solution Overview
Problem
Testing of stacked semiconductor memory apparatuses is challenging due to limited pin count, making it difficult to perform individual tests on each die, which complicates diagnosing operational issues.
Innovation Solution
A semiconductor memory apparatus with a delay control unit that generates delayed test control signals for each stacked semiconductor die, allowing them to operate in synchronized or staggered test modes, enabling simultaneous testing of different operations across multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple stacked semiconductor dies are tested simultaneously using limited pins, then testing capacity is improved, but individual die testing capability deteriorates
Solution Approach 1:
The patent segments the testing process by introducing separate normal signal transfer paths and test signal transfer paths. This allows different signaling modes (normal operation vs. test mode) to be independently controlled for each semiconductor die, enabling individual die testing even when multiple dies are stacked together with limited pin availability.
Solution Approach 2:
The patent implements dynamic signal routing where the same physical pins can be dynamically allocated to different functions. By using control signals to switch between normal operation mode and test mode, the system can adaptively reconfigure pin assignments to support either simultaneous multi-die operation or individual die testing as needed.
2Speed
If stacked semiconductor dies operate independently to improve response speed, then operational performance is improved, but testability deteriorates
Solution Approach 1:
The patent introduces intermediary control mechanisms including test mode signals and delay control units that mediate between the independent operation requirements and testing requirements. These intermediaries enable coordinated testing of independently operating dies by providing synchronized control without compromising their independent operational capability during normal use.
Solution Approach 2:
The patent applies preliminary action by implementing delay control units that pre-adjust signal timing before tests are executed. This allows the test system to proactively synchronize test signals across multiple independently operating dies, ensuring proper timing alignment is established before actual testing begins, thereby facilitating testability without affecting operational independence.
3Device complexity
If test control signals are applied uniformly to all stacked dies, then simple control is achieved, but individual die timing control capability deteriorates
Solution Approach 1:
The patent implements self-service by enabling each semiconductor die to independently process and respond to test control signals according to its specific timing requirements. Each die can autonomously adjust its internal timing based on received control signals, eliminating the need for complex external timing coordination while maintaining individual die timing control capability.
Solution Approach 2:
The patent utilizes parameter changes by allowing test control signals to carry different timing parameters for different dies. The delay control units can modify signal timing parameters (such as delay duration) based on which die is being tested, enabling flexible individual die timing control through parameter variation rather than structural complexity.
Data Source
AI summary
A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.