Semiconductor Test Data Alignment Circuit for Limited I/O Pads
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Solution Overview
Problem
The limited number of data input/output pads in semiconductor apparatuses complicates the process of writing a desired test pattern across all connected pads during the testing process, leading to difficulties in achieving high test yield.
Innovation Solution
Incorporating a data alignment circuit and data pattern control circuits within the semiconductor apparatus to align and adjust data patterns across multiple input paths connected to data input/output pads, enabling efficient generation and writing of test data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of data input/output pads allocated to each DUT is reduced to increase test yield, then test yield is improved, but the ability to write desired test patterns across all pads deteriorates
Solution Approach 1:
The patent combines data from multiple data input/output pads into a single aligned data stream through the data alignment circuit. This merging allows test patterns to be written efficiently through limited pads while still utilizing all pads for testing, thereby maintaining high test yield without sacrificing pattern writing capability
Solution Approach 2:
The data alignment circuit acts as an intermediary between the limited data input/output pads and the memory device. It receives data from multiple pads, aligns them properly, and generates the desired test patterns, thus mediating between the constraint of limited pads and the requirement for comprehensive pattern writing
2Productivity
If data is input through multiple data input/output pads simultaneously, then test efficiency is improved, but data alignment and pattern control complexity increases
Solution Approach 1:
The patent segments the data alignment and pattern control functions into distinct dedicated circuits: a data alignment circuit for aligning data from multiple pads, and a data pattern control circuit for generating test patterns. This segmentation manages complexity by separating concerns while maintaining efficient simultaneous pad utilization
Solution Approach 2:
The data alignment circuit automatically aligns data from multiple pads without requiring external intervention, and the data pattern control circuit autonomously generates appropriate test patterns based on the aligned data. This self-service capability reduces operational complexity while maintaining high test efficiency
Data Source
AI summary
A semiconductor apparatus includes a data alignment circuit and a data pattern control circuit. The data alignment circuit aligns data input through each of a plurality of data input/output pads to generate a plurality of alignment data. The data pattern control circuit generates a plurality of preliminary write data by copying some bits of a first alignment data among the plurality of alignment data to a plurality of input paths coupled to data input/output pads other than a first data input/output pad among the plurality of data input/output pads, and changes a pattern of the plurality of preliminary write data according to remaining bits of the first alignment data to generate a plurality of write data.