Model Checker Integrated Circuit Verification Traces
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Solution Overview
Problem
Conventional verification methods for integrated circuits are time-consuming and inaccurate due to the complexity of simulating large and complex system-on-chip designs, and lack control and visibility over critical signals, leading to difficulties in verifying and debugging actual hardware circuits.
Innovation Solution
A system and method that uses a Model Checker in conjunction with an integrated circuit under test (ICUT) to analyze user logic, incorporating a user logic region and a debug logic region with reconfigurable logic, allowing for direct processing on an actual chip to provide control and visibility, and generating ICUT-based traces for assertion evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional software simulation tools are used to verify circuit design, then verification can be performed before fabrication, but the process becomes increasingly time consuming and complex for large system-on-chip designs
Solution Approach 1:
The verification system is segmented into multiple components: a Model Checker for formal verification of critical properties, a simulator for behavioral verification, and a testbench framework. This segmentation allows each tool to focus on specific aspects of verification, improving overall efficiency and accuracy while reducing the time burden of comprehensive verification.
Solution Approach 2:
A testbench framework acts as an intermediary between the design under verification and both the Model Checker and simulator. This intermediary layer standardizes the interface and coordination between different verification tools, enabling efficient collaboration and reducing the complexity of integrating multiple verification approaches.
2Loss of time
If simulation of high levels of abstraction is used, then verification can be performed early in design, but accuracy with regard to physical circuit cannot be guaranteed
Solution Approach 1:
The system performs preliminary formal verification using the Model Checker on high-level abstract models to identify and correct design errors early in the design process. This preliminary action catches logical errors before physical fabrication, saving time and cost while maintaining accuracy through formal methods that are independent of simulation fidelity.
Solution Approach 2:
The verification approach dynamically adapts to different design stages: using formal verification methods for early abstract model validation and transitioning to simulation-based verification as the design matures. This dynamic approach ensures accuracy at each stage while optimizing the overall verification timeline.
3Reliability
If silicon debug is used to verify actual hardware circuit, then physical circuit can be verified, but control and visibility over critical signals are lacking making debugging difficult and costly
Solution Approach 1:
The system incorporates automated feedback mechanisms where the Model Checker continuously monitors critical signals and properties during verification, providing immediate feedback about assertion violations. This automated feedback replaces manual silicon debugging by systematically tracking signal states and reporting errors with precise location information, making hardware verification easier and more efficient.
4Reliability
If Model Checker explores entire reachable state space, then complete verification can be achieved, but state explosion problem prevents finishing exploration for complex integrated circuits
Solution Approach 1:
The system applies partial verification by focusing the Model Checker on specific critical properties and state spaces that are most important for correctness, rather than attempting to verify the entire state space. This selective approach achieves sufficient verification completeness for critical functions while maintaining productivity by avoiding exploration of irrelevant state spaces.
Solution Approach 2:
The verification effort is distributed with different quality levels applied to different parts of the design: formal verification with high thoroughness is applied to critical safety and correctness properties, while less critical functions use lighter verification approaches. This local quality differentiation ensures reliability where needed while maintaining overall productivity.
Data Source
AI summary
A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model Checker and a fabricated integrated circuit under test (ICUT), to increase the state space which is explored. ICUT-based traces from the integrated current are generated, in part based on initial states and assertions provided by the Model Checker or by a user. The Model Checker verifies the integrated circuit by generating Model Checker-based traces from basic logic, which are reproductions of the ICUT-based traces.