On-Chip Oscillator for At-Speed Delay Fault Testing
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Solution Overview
Problem
As digital semiconductor IC geometries shrink and signal speeds increase, fault testing becomes more challenging due to issues like marginal contacts and interconnects causing signal delay faults, and existing methods for at-speed delay fault testing are complex and costly, especially when transitioning from wafer-level to packaged IC testing.
Innovation Solution
An integrated circuit sensor generates a master clock signal to produce a test clock signal with precise launch and capture pulses, coinciding with the master clock signal edges, using an oscillator already on the chip, which allows for accurate delay fault testing without significant additional circuitry or ATE complexity, and adjusts pulse spacing through a trim signal generated from programming signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If at-speed delay fault testing is performed with precise launch/capture clock signals, then measurement precision is improved, but device complexity increases due to potentiometer adjustment mechanisms
Solution Approach 1:
The DUT interface board generates its own test clock signal using an on-board oscillator, eliminating the need for external ATE to provide precise launch/capture clock signals. The interface board self-adjusts the clock signal parameters through digital control signals, making the system self-sufficient and reducing external complexity
Solution Approach 2:
The mechanical potentiometer adjustment mechanism is replaced with a digital control system. The interface board uses digital control signals to programmatically adjust the oscillator frequency and timing parameters, replacing manual mechanical adjustment with electronic digital control
2Productivity
If wafer level testing is used for delay fault testing, then productivity is improved, but reliability worsens due to faults occurring after packaging
Solution Approach 1:
The DUT interface board is designed to perform multiple testing functions - it can conduct both wafer-level testing and packaged IC-level testing using the same hardware platform. The board generates test patterns, provides stimulus signals, and captures responses for both testing scenarios, making the system universal and eliminating the need for separate testing equipment
3Reliability
If device level testing is performed for packaged ICs, then reliability is improved, but device complexity increases due to more complex DUT boards
Solution Approach 1:
The DUT interface board generates its own precise test clock signal using an on-board oscillator, eliminating the need for complex external ATE timing control. The board self-manages the launch/capture clock signal generation, reducing the complexity burden on the external testing equipment
Solution Approach 2:
The testing functionality is segmented into modular components within the interface board - the oscillator module, the pattern generation module, and the response capture module operate independently but coordinate through digital control signals. This modular segmentation reduces overall system complexity while maintaining comprehensive testing capability
Data Source
AI summary
An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.