Semiconductor Device Interface Control Circuit for Marching Test
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Solution Overview
Problem
In semiconductor devices with large bit widths, it is challenging to perform a marching test on RAMs with only a row address assigned, as all memory cells in the row direction become selected, making it difficult to isolate adjoining memory cells and requiring exclusive-use test patterns, which increases costs.
Innovation Solution
A semiconductor device with a memory cell array, bit-line pairs, input/output circuits, and an interface control circuit that selectively controls data input/output during normal and test modes, allowing for the execution of a marching test without the need for an exclusive-use test pattern by alternately selecting even and odd-numbered memory cell columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a marching test is executed on a RAM with only row address assigned (large bit width), then the test can detect inter-cell interference, but all memory cells in the row direction become selected making it difficult to isolate adjoining memory cells
Solution Approach 1:
The patent divides the memory cell array into multiple banks (first bank and second bank) along the column direction. By selecting specific banks based on the least significant bit of the column address, the test can isolate adjoining memory cells even in large bit width configurations. This segmentation allows the marching test to proceed effectively by preventing all cells in a row from being simultaneously selected.
2Reliability
If a pseudo marching test is executed using a special test pattern, then the test can be performed on large bit width RAM, but an exclusive-use test pattern must be mounted in the BIST circuit increasing cost
Solution Approach 1:
The patent makes the existing BIST circuit capable of performing both normal memory operations and marching tests using the same circuit structure. By utilizing the bank selection mechanism that already exists for normal operations, the marching test can be executed without requiring exclusive-use test patterns or additional dedicated test hardware, thereby reducing BIST circuit complexity and cost.
3Productivity
If all memory cells in a row are selected by row address assignment, then data can be accessed efficiently, but it becomes impossible to bring only the adjoining memory cell into an un-selected state
Solution Approach 1:
The memory cell array is segmented into multiple banks along the column direction. The bank selection is controlled by the least significant bit of the column address, allowing selective access to specific banks while keeping other banks in an un-selected state. This enables the system to maintain efficient data access within selected banks while isolating adjoining memory cells in un-selected banks for testing purposes.
Data Source
AI summary
A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.