Integrated Circuit Testing Path Selection for Multi-Chip Package Fault Identification
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Solution Overview
Problem
Integrated circuit dies within multi-chip devices face reduced testability due to limited access to pins, making it challenging to perform effective testing and fault identification after they are incorporated into larger systems.
Innovation Solution
A system and method where each integrated circuit die includes a testing circuit with both a testing path and a bypass path, along with control circuitry that selects between these paths to facilitate the transmission of test stimulus and results data, allowing for sequential testing of interconnected dies without direct external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integrated circuit dies are incorporated into larger systems (multi-chip devices), then system functionality and integration are improved, but testability and access to pins are reduced
Solution Approach 1:
The patent introduces an intermediary testing circuit within each die that includes both a testing path and a bypass path. This intermediary structure allows test signals to be routed through neighboring dies when direct pin access is unavailable, effectively mediating the testing process for internally located dies in the multi-chip system.
Solution Approach 2:
The testing circuit is segmented into two distinct paths: a testing path for applying test patterns and detecting faults, and a bypass path for routing test signals to adjacent dies. This segmentation enables flexible signal routing that overcomes the pin accessibility limitations in integrated systems.
2Ease of operation
If direct external connections are provided to all integrated circuit dies, then testability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The testing circuit is designed with multi-functionality to handle multiple testing scenarios. The same circuit structure with its dual paths (testing and bypass) can route signals to different destinations depending on the test configuration, eliminating the need for separate dedicated test connections for each die while maintaining comprehensive testability.
3Reliability
If sequential testing of interconnected dies is implemented, then test coverage is improved, but testing time and complexity increase
Solution Approach 1:
The bypass path enables continuous testing operation by allowing test signals to be routed through non-tested dies to reach tested dies, and vice versa. This continuous signal routing capability ensures that testing can proceed without interruption and that all dies can be tested systematically in sequence without requiring complete system disassembly or reconfiguration.
Data Source
AI summary
Systems and methods are provided for an integrated circuit system. A plurality of separate integrated circuit dies are coupled together to form an integrated circuit package, a first integrated circuit die including an input and a last integrated circuit die including an output, ones of the plurality of integrated circuit dies including a testing circuit associated with a corresponding integrated circuit die. The testing circuit includes a testing path for testing functionality of the corresponding integrated circuit die, a bypass path bypassing the testing path, and control circuitry for selecting between an output of the testing path and an output of the bypass path, the control circuitry being configured to select the output of the testing path or the output of the bypass path and to pass the selected output to a subsequent integrated circuit die among the plurality of coupled circuit dies.