Integrated Circuit Timing Analysis Simplified Netlist Generation
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Solution Overview
Problem
Traditional timing analysis approaches for integrated circuits, especially analog and mixed signal circuits, are complex and time-consuming, often failing to accurately locate timing errors when simulations are performed with incorrect patterns, leading to potential malfunctions.
Innovation Solution
A computer program product for IC timing analysis that includes a netlist reading module, a signal path analysis module, and a clock delay calculating module, which simplifies the analysis by generating a simplified netlist and calculating clock delays for non-standard cell elements, replacing certain circuit blocks with impedance loads to reduce complexity and maintain accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional simulation analysis is performed for timing analysis, then accuracy of timing error location is improved, but analysis time and complexity increase significantly
Solution Approach 1:
The patent extracts only the critical timing paths from the complete circuit simulation. By identifying and isolating the signal paths that affect timing accuracy (those passing through circuit blocks with non-standard cells), the system performs targeted analysis rather than full-circuit simulation, thereby reducing analysis time while maintaining accuracy for the critical timing errors.
Solution Approach 2:
The patent segments the timing analysis process into distinct modules: netlist reading, signal path analysis, and clock delay calculation. Each module handles a specific aspect of the timing analysis independently, allowing for optimized processing of each segment and reducing the overall computational burden compared to monolithic simulation approaches.
2Measurement precision
If traditional simulation analysis is performed for timing analysis, then timing error location accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts and focuses analysis on only the critical timing paths that pass through circuit blocks with non-standard cells. By filtering out non-critical paths and performing full simulation only on the extracted critical paths, the system reduces the complexity of the analysis process while maintaining accuracy for timing error location.
Solution Approach 2:
Instead of performing comprehensive simulation on the entire circuit and then filtering results (traditional approach), the patent inverts the process by first identifying critical timing paths and then performing targeted analysis only on those paths. This inversion fundamentally reduces the complexity of the analysis process.
3Productivity
If incorrect clock patterns are used in simulation, then analysis speed is improved, but timing error detection accuracy deteriorates
Solution Approach 1:
The patent incorporates feedback mechanisms where the clock delay calculation module uses the simplified netlist and circuit block information to compute accurate clock delays for each signal path. This feedback loop ensures that even when using optimized analysis patterns, the system can detect timing errors accurately by comparing actual measured delays against the calculated expected delays from the simplified model.
Data Source
AI summary
A computer program product stored in a non-transitory storage device of an integrated circuit (IC) timing analysis device includes: a netlist reading module for reading a netlist of an integrated circuit; a signal path analysis module for analyzing signal paths of a clock signal to generate a simplified netlist of the integrated circuit; a clock delay calculating module for calculating clock delays of the clock signal respectively corresponding to the signal paths.