IGBT Base Region Impurity Gradient for Low ON Voltage
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Solution Overview
Problem
IGBT semiconductor devices face a trade-off between withstand voltage and ON voltage, with methods to reduce ON voltage often lowering withstand voltage, and are prone to latch-up phenomena due to parasitic transistors.
Innovation Solution
A semiconductor device structure with a p-type collector region, n-type drift region, and a p-type base region, where the base region has a shallower lower surface in contact with the gate oxide film and higher impurity concentration further from the film, reducing ON voltage while maintaining high withstand voltage and suppressing latch-up by controlling channel length and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the impurity concentration of the carrier accumulation layer is raised to reduce ON voltage, then the ON voltage is reduced, but the withstand voltage is lowered because it becomes difficult to extend the depletion layer
Solution Approach 1:
The base region is designed with non-uniform impurity concentration distribution, where the impurity concentration is higher in the region closer to the emitter region and lower in the region closer to the drift region. This local quality variation allows the base region to simultaneously achieve low ON voltage (through higher impurity concentration near emitter for better carrier injection) and high withstand voltage (through lower impurity concentration near drift region for extended depletion layer)
Solution Approach 2:
The invention changes the impurity concentration parameter along the depth direction of the base region. By controlling the impurity concentration to decrease from the emitter side toward the drift region, the patent resolves the trade-off between ON voltage and withstand voltage, achieving both low ON voltage and high breakdown voltage
2Use of energy by stationary object
If a carrier accumulation layer is formed between base region and drift region to reduce ON voltage, then the ON voltage is reduced, but latch-up phenomenon occurs due to generation of parasitic transistors
Solution Approach 1:
The base region employs non-uniform impurity concentration distribution with higher concentration near the emitter and lower concentration near the drift region. This local quality control suppresses parasitic transistor generation by optimizing carrier distribution, thereby preventing latch-up phenomenon while maintaining low ON voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves a balance of low ON voltage and high withstand voltage while minimizing latch-up occurrences through controlled channel formation and impurity concentration gradients.
Implementation Method 1
oxidizing an inner wall of the trench and forming a gate oxide film, thereby taking, into the gate oxide film, p-type impurities from an area of the base region in contact with the gate oxide film
Data Source
AI summary
A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film.