IGBT Cell Structure Eliminating Parasitic Thyristor Latch-Up
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Insulated gate bipolar transistors (IGBTs) face reliability issues due to parasitic thyristor latch-up, excessive junction temperature, high dv/dt and di/dt conditions, and oxide layer breakdown, leading to reduced safe operating area and increased risk of failure.
Innovation Solution
A semiconductor device with a novel cell structure featuring N-type and P-type regions, trench units, and electric field shielding regions, which includes a gate region isolated by dielectric material, providing a large safe operating area, high short-circuit withstand time, low gate-collector charge, and reduced on-voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional IGBT structure is used, then device can operate in rated state, but parasitic thyristor latch-up occurs and reliability decreases under extreme conditions
Solution Approach 1:
The patent extracts and eliminates the parasitic thyristor structure by modifying the conventional IGBT cell design. By removing the P-type body region that forms the parasitic thyristor with the N- drift region, the latch-up effect is completely eliminated while maintaining the desired IGBT functionality.
Solution Approach 2:
The patent applies local quality by creating different doping profiles and structural characteristics in specific regions of the device. The N-type drift region is designed with optimized doping concentration and depth to prevent parasitic thyristor formation, while other regions maintain their conventional structures for proper IGBT operation.
2Reliability
If conventional IGBT structure is used, then device has standard performance, but safe operating area is limited under high voltage and current conditions
Solution Approach 1:
The patent changes critical parameters including the doping concentration of the N-type drift region, the depth of the P-type collector region, and the thickness of the oxide layer. These parameter optimizations enable the device to withstand higher voltages and currents simultaneously, expanding the safe operating area.
Solution Approach 2:
The patent employs a composite structure combining different semiconductor materials and dielectric layers with optimized properties. The combination of silicon-based semiconductor regions with carefully engineered oxide insulation layers creates a device that can handle extreme voltage and current conditions.
3Speed
If conventional IGBT structure is used, then device has standard switching speed, but turn-off loss increases under high di/dt conditions
Solution Approach 1:
The patent optimizes the dynamic characteristics of the device by adjusting the doping profiles to control carrier distribution during switching transitions. The modified structure enables faster extraction of carriers during turn-off, reducing tail current and associated losses while maintaining high switching speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a large safe operating area, high short-circuit withstand time, eliminates parasitic thyristor effects, and reduces on-voltage drop while maintaining low process complexity and high reliability.
Implementation Method 1
a first dielectric being provided between the gate region and semiconductor material for isolation
Implementation Method 2
at least one N-type carrier barrier region having a doping concentration higher than that of the N-type substrate
Implementation Method 3
at least one P-type electric field shielding region; wherein the N-type carrier barrier region is provided with a surface in direct contact with the first trench unit, the N-type carrier barrier region is further provided with a surface in direct contact with the second trench unit, and the P-type electric field shielding region is provided with a surface in direct contact with the second trench unit
Implementation Method 4
Insulated gate bipolar transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device consisted of a metal-oxide-semiconductor (MOS) field effect transistor and a bipolar junction transistor (BJT), having the advantages of high input impedance, small driving power, simple driving circuit, fast switching speed and low on-voltage drop
Data Source
AI summary
A semiconductor device comprises at least one cell. The structure of each cell comprises: a N-type substrate; at least one first trench unit and at least one second trench unit provided on one side of the N-type substrate; at least one P-type semiconductor region provided on the other side of the N-type substrate, the P-type semiconductor region consisting an anode region; at least one N-type carrier barrier region; and at least one P-type electric field shielding region. The purpose of the present invention is to provide a semiconductor device which has a novel cell structure to provide: a large safe operating area; a short-circuit resistance; elimination of the effect of parasitic thyristors; a low gate-collector charge (QGC) to provide a maximum resistance to dv/dt; increase of conductivity modulation at the emitter side to provide a large current density and an extremely low on-voltage drop; a small turn-off loss; and a low process complexity.