Trench IGBT Floating Region Segmentation for Voltage Trade-off

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Solution Overview

Problem

Conventional trench-type IGBTs face a trade-off between maintaining high withstand voltage and low ON-voltage, where deepening the p-type floating layer for higher withstand voltage thickens the p-type base layer, increasing ON-voltage, and thinning the base layer for lower ON-voltage compromises withstand voltage.

Innovation Solution

The semiconductor device features a p-type floating region formed deeper than the p-type base region, with an overlap portion extending to the bottom of the emitter trench, allowing for reduced collector-emitter voltage and improved withstand voltage while maintaining a shallow p-type base region, and includes a dummy trench for simplified manufacturing and enhanced contact area, allowing for miniaturization of the trench structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the p-type floating layer is deeply diffused to maintain high withstand voltage, then the withstand voltage is improved, but the p-type base layer becomes thickened and ON-voltage increases

Engineering Contradiction:
Improvewithstand voltageVSAvoidON-voltage
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent divides the p-type region into two distinct segments: a p-type base layer and a p-type floating layer. The p-type base layer is kept thin to maintain low ON-voltage, while the p-type floating layer is extended deeply to ensure high withstand voltage. This segmentation allows each layer to be optimized independently for its specific function, resolving the contradiction between low ON-voltage and high withstand voltage requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different depth characteristics to different regions of the p-type structure. The p-type base layer near the surface is thin with lower depth to reduce ON-voltage, while the p-type floating layer extends deeply into the drift region to provide high withstand voltage. This local differentiation of quality (depth) allows simultaneous optimization of both voltage characteristics.

Inventive Principle:
Principle #3Local quality

2Power

If the p-type base layer is thinned to reduce ON-voltage, then ON-voltage is improved, but withstand voltage becomes difficult to maintain

Engineering Contradiction:
ImproveON-voltageVSAvoidwithstand voltage
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

By segmenting the p-type region into a thin base layer and a deep floating layer, the patent enables the base layer to be thinned for low ON-voltage while the floating layer compensates by extending deeply to maintain withstand voltage. The segmentation allows functional separation where each layer addresses specific voltage requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extends the p-type floating layer in the depth dimension beyond the p-type base layer. This dimensional extension into the drift region provides the necessary withstand voltage capability without requiring increased base layer thickness, thus maintaining low ON-voltage while achieving high breakdown voltage through vertical extension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10923582B2Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region
Publication Date: 2021.02.16 ROHM CO LTD
  • US10923582B2 patent drawing
  • US10923582B2 patent drawing
  • US10923582B2 patent drawing

AI summary

A semiconductor device is disclosed having a plurality of gate trenches formed on the surface thereof, each filled with a gate insulating film and a gate electrode. A transistor region is defined between adjacent gate trenches forming a pair, and includes an n+-type emitter region, a p-type base region, and an n−-type drift region disposed lateral to each gate trench in the pair, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer. A p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region. A plurality of emitter trenches are formed one either side of each of the gate trenches in the pair of gate trenches.