IGBT Gate Electrode Recessing for Capacitance Reduction
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Solution Overview
Problem
In semiconductor devices with GGEE structures, shrinking cell size to reduce on-voltage is challenging due to difficulties in forming emitter potential contact holes within active cell regions, and increased trench density leads to deteriorated switching characteristics from increased capacitance.
Innovation Solution
The semiconductor device features a GGEE structure with first and second trenches, a base region, emitter regions, and contact holes positioned to avoid contact with the gate electrodes, along with a recessed gate electrode in the trench to reduce capacitance and improve miniaturization, while maintaining effective emitter potential application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cell size is shrunk to reduce on-voltage, then device performance is improved, but it becomes difficult to form contact holes for emitter potential in active cell areas
Solution Approach 1:
The patent positions contact holes at locations overlapping trenches in plan view, utilizing the vertical dimension to resolve the horizontal space constraint. By forming contact holes that extend through insulating films to reach semiconductor regions at trench locations, the invention enables contact hole formation in shrunk cell structures without requiring additional horizontal space that would conflict with trench gate positions.
2Productivity
If trench density is increased to shrink cells, then cell size is reduced, but gate capacitance increases and switching characteristics deteriorate
Solution Approach 1:
The patent extracts the gate electrode from portions of trenches that overlap with contact hole positions. By removing gate electrodes from specific trench regions and forming insulating films in their place, the invention reduces the total gate capacitance while maintaining high trench density for cell shrinkage. This selective extraction of gate structures eliminates parasitic capacitance contributions from overlapping regions.
3Reliability
If contact holes are positioned to avoid gate electrodes, then proper emitter potential application is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent forms insulating films in trenches at predetermined locations before forming contact holes. This preliminary action defines the positions where contact holes should be formed and ensures they will not contact gate electrodes. By pre-establishing the insulating film pattern, the invention simplifies subsequent contact hole formation processes and reduces the risk of manufacturing defects.
Data Source
AI summary
An IGBT with improved switching characteristics is disclosed. The contact hole CH1 in which the emitter potential electrode EE is buried is formed at a position overlapping with the trench T 1 in which the gate electrode G 1 is buried in plan view. The upper surface of gate electrode G1 in trench T1 is retracted, and an interlayer insulating film IL2 is formed on the top of trench T1. Since the bottom of the contact hole CH1 is located on the interlayer insulating film IL2 in the trench T 1 and in the base region PB, the emitter potential electrode EE is not in contact with the gate electrode G 1.