IGBT with Modified Drain Contact for High Frequency LDMOS
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Solution Overview
Problem
High voltage and high current LDMOS transistors face limitations in high frequency performance due to high input-capacitance varying with gate voltage, and existing series combinations with silicon MOSFET and JFET are difficult to integrate with low voltage control functions, requiring efficient cooling and being prone to latch-up.
Innovation Solution
A novel insulated gate bipolar transistor device is created by connecting a first insulated gate field effect transistor in series with a second field effect transistor, featuring a modified drain contact region, which reduces on-resistance, increases current capacity, and eliminates latch-up, allowing operation at lower power with reduced input capacitance and improved high frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate overlap over drift region is increased to achieve high current and low on-resistance, then current capability is improved, but input-capacitance increases significantly limiting high frequency performance
Solution Approach 1:
The device is divided into two separate field effect transistors connected in series: a first FET with modified drain contact and a second FET with standard structure. This segmentation allows each transistor to be optimized independently - the first for low on-resistance with reduced gate overlap and the second for high current capability - thereby resolving the contradiction between current capability and high frequency performance.
2Power
If series combination of silicon MOSFET and JFET is used to achieve high voltage and high current, then voltage and current capability are improved, but integration with low voltage control functions becomes difficult and cooling requirements increase
Solution Approach 1:
Two field effect transistors are combined in a series configuration within a single integrated device structure, merging high voltage/high current capability with low voltage control functions in one component. This integration eliminates the need for separate discrete devices and complex cooling systems, reducing overall device complexity while maintaining high power capability.
3Power
If high voltage operation is implemented in series MOSFET-JFET combination, then voltage capability is improved, but latch-up susceptibility increases and efficient cooling is required
Solution Approach 1:
The first field effect transistor is given a specialized local structure with modified drain contact region featuring a first conductivity type region surrounded by a second conductivity type region. This localized structural modification optimizes the high voltage region to prevent latch-up while maintaining overall device integration and reducing cooling requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher current capability, lower on-resistance, and reduced power consumption within a given area, while being immune to latch-up, thus enhancing reliability and frequency performance by minimizing the electric field near the gate and reducing the need for additional voltage sources.
Implementation Method 1
a first conductivity type drain contact region (16) surrounded by a second conductivity type region (10)
Data Source
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AI summary
An insulated gate bipolar transistor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET (2), wherein the second field effect transistor (2) has a modified drain contact region (16) of opposite conductivity to the pocket (11) surrounding it, and has a heavily doped source contact region (16A) which is electrically connected to a heavily doped drain contact region (161) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).