IGBT N-Buffer Layer Laser Annealing for Switching Speed
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Solution Overview
Problem
Light-punch-through type IGBTs face challenges in maintaining high destruction resistance during short-circuit tests and achieving elevated switching speed while minimizing ON voltage fluctuations, due to the trade-off between ON voltage and switching speed in existing designs.
Innovation Solution
The method involves forming highly and lowly activated portions in the N-buffer layer using laser annealing treatments, with the direction of these activations alternated in stripes to control hole injection efficiency and field intensity, thereby enhancing switching speed and preventing destruction resistance reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the concentration in the P-collector layer is lowered to elevate switching speed, then the switching speed is improved, but the destruction resistance is lowered and ON voltage fluctuation increases
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations within the P-collector layer. Specifically, it forms a high-concentration P-collector layer adjacent to the N-buffer layer and a low-concentration P-collector layer adjacent to the N--drift layer. This spatial variation in concentration allows the high-concentration region to provide destruction resistance while the low-concentration region enables fast switching speed, resolving the contradiction between these two opposing requirements.
Solution Approach 2:
The P-collector layer is segmented into multiple regions with different impurity concentrations. The patent divides the P-collector layer into a first P-collector layer (high concentration) and a second P-collector layer (low concentration), each serving different functional purposes. This segmentation allows simultaneous optimization of both destruction resistance and switching speed in different parts of the same layer.
2Speed
If the concentration in the P-collector layer is lowered to elevate switching speed, then the switching speed is improved, but the ON voltage fluctuation increases
Solution Approach 1:
The patent uses local quality to stabilize ON voltage by creating a high-concentration P-collector layer region adjacent to the N-buffer layer. This high-concentration region provides stable hole injection characteristics that reduce ON voltage fluctuation, while allowing other regions to maintain low concentration for fast switching speed.
3Speed
If the IGBT is designed for high switching speed with low P-collector concentration, then the switching speed is improved, but the field intensity becomes excessively high in short-circuit state
Solution Approach 1:
The patent applies local quality by forming a high-concentration P-collector layer region adjacent to the N-buffer layer that acts as a field-intensity-control region. This local high-concentration region limits excessive field intensity buildup during short-circuit conditions, while allowing low-concentration regions to maintain fast switching performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively elevates switching speed and stabilizes ON voltages, preventing destruction resistance lowering during short-circuit tests by optimizing hole injection and field intensity management.
Implementation Method 1
performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe
Implementation Method 2
performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer
Data Source
AI summary
A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.