3D IGFET Power Routing Layout for ESD Protection and Compact ICs
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Solution Overview
Problem
Integrated circuits face challenges with power supply potential fluctuations due to high resistivity interconnects, excessive IC real estate consumption by ESD protection, and inefficient routing, which affect circuit compactness and functionality.
Innovation Solution
The implementation of insulated gate field effect transistors (IGFETs) with alternating conductivity types and buried conductive lines, connected via through vias, to efficiently route power supply voltages and provide ESD protection, optimizing circuit layout and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power supply routing is used, then power supply can be delivered to circuits, but supply potential integrity deteriorates due to high resistivity interconnect
Solution Approach 1:
The patent introduces a third dimension by forming conductive lines and vias that extend through the thickness of the substrate. Power supply voltage is routed through conductive lines in the second substrate surface and through vias to circuits, creating a vertical (z-axis) routing path that reduces the horizontal (x-y plane) interconnect length and resistance, thereby improving supply potential integrity.
Solution Approach 2:
The power supply routing is segmented into multiple components: conductive lines formed in the second substrate surface, through vias extending through the substrate, and connections to circuits. This segmentation allows optimized routing paths and reduces the resistance of individual interconnect segments, improving overall power delivery integrity.
2Reliability
If ESD protection circuits are implemented, then electrostatic discharge protection is provided, but IC real estate consumption increases prohibitively
Solution Approach 1:
The patent merges ESD protection functionality with the power supply routing infrastructure. ESD protection circuits are implemented using the same conductive lines and through vias that are already present for power delivery, eliminating the need for separate dedicated ESD protection routing and reducing overall IC real estate consumption.
Solution Approach 2:
The conductive lines and through vias serve multiple functions: they provide power supply voltage delivery to circuits and simultaneously serve as routing paths for ESD protection circuits. This multi-functionality reduces the total amount of dedicated ESD protection structure required, minimizing IC real estate usage.
3Ease of operation
If power supply and signal routing is implemented, then circuits can be powered and signaled, but IC real estate consumption becomes excessive compared to active devices
Solution Approach 1:
By utilizing the vertical dimension through through vias that extend through the substrate thickness, the patent enables power and signal routing without consuming excessive horizontal space. This 3D routing approach allows compact circuit layouts while maintaining full routing functionality.
Solution Approach 2:
The patent changes the routing parameter from horizontal interconnect length to vertical via depth. By optimizing the via dimensions and spacing, efficient power and signal delivery is achieved with minimal horizontal footprint, reducing the ratio of routing area to active device area.
Data Source
AI summary
A method can include receiving a first power supply voltage at a first terminal substantially at a first side of an IC device; providing first and second rows of insulated gate field effect transistors (IGFETs) substantially at a second side of the IC device, each IGFET including first and second source/drains (S/Ds), channels, and a control gate that substantially surrounds the channels. A first power supply voltage can be coupled from the first terminal to an S/D of an IGFET in the first row via a first conductive via disposed between the first side and the second side and a first conductive line buried in and proximate the second side. IGFETs of the first row can have a first conductivity type. IGFETs of the second row can have a second conductivity type. Corresponding devices and systems are also disclosed.