Power IGFET Trench Snubber for Ringing Reduction
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Solution Overview
Problem
Power insulated-gate field-effect transistors (IGFETs) experience ringing issues due to interactions between package inductance and circuit board non-linear output capacitance, which worsen with advancements in technology requiring faster switching speeds and lower on-state resistance, and existing integrated snubber structures are insufficient to address these challenges.
Innovation Solution
The design incorporates doped regions and trenches between them, with a conductive member within the trench to repel charge carriers and a high dopant concentration at the trench bottom or sidewalls to maintain low leakage current, and a compensation region with a low average net dopant concentration to control capacitance, allowing for efficient switching operations without significant additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If faster switching speeds and lower on-state resistance are implemented in power IGFETs, then efficiency is improved, but capacitance characteristics worsen leading to increased ringing
Solution Approach 1:
The patent extracts the snubber function from an external separate component and integrates it directly into the transistor structure by forming doped regions within the transistor body. This integration allows the snubber to be co-located with the power IGFET, enabling faster switching speeds while the extracted snubber function compensates for worsened capacitance characteristics by providing controlled charge storage and discharge paths, thereby reducing ringing effects
Solution Approach 2:
The patent implements nesting by placing the snubber doped regions inside the transistor structure itself. The snubber n-type doped region is formed within the drift region, and the snubber p-type doped region is formed within the body region, creating a nested configuration where the snubber function is embedded within the transistor. This nested design allows the snubber to directly interact with the transistor's electric fields and capacitance, compensating for worsened capacitance characteristics while maintaining fast switching performance
2Reliability
If integrated snubber structures are added to modern shielded-gate IGFETs, then ringing is reduced, but device complexity increases
Solution Approach 1:
The patent merges the snubber function with the transistor structure by forming doped regions that serve dual purposes. The snubber n-type doped region is formed in the drift region using the same doping processes as the transistor, and the snubber p-type doped region is formed in the body region using existing p-type doping steps. This merging approach integrates the snubber into the transistor without requiring separate fabrication processes, thereby reducing device complexity while achieving ringing reduction
Solution Approach 2:
The patent implements multi-functionality by designing doped regions that serve multiple functions simultaneously. The n-type doped region in the drift region acts as both the transistor's drift region for voltage blocking and as the snubber's charge storage region. The p-type doped region serves as both the transistor's body region and as the snubber's opposing polarity region. This universal design allows a single structure to provide both transistor operation and snubber ringing reduction functions, simplifying the overall device
3Area of stationary object
If doped regions are placed close to each other to reduce area, then isolation becomes difficult, but larger area increases device size
Solution Approach 1:
The patent applies local quality by creating highly localized doped regions with specific dopant concentrations and spatial distributions. The snubber n-type doped region is formed with a peak dopant concentration of 1×10^19 to 1×10^21 atoms/cm³ in a specific depth range, while the snubber p-type doped region is formed with a peak dopant concentration of 1×10^18 to 1×10^20 atoms/cm³. These localized doped regions provide strong electric field confinement and charge storage capability in small volumes, achieving both area reduction and reliable isolation through precise local doping control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces ringing and maintains low leakage current, effectively addressing the capacitance challenges and ensuring reliable high-speed switching operations in power transistors.
Implementation Method 1
a conductive member within the trench to repel charge carriers
Implementation Method 2
a high dopant concentration at the trench bottom or sidewalls to maintain low leakage current
Implementation Method 3
a compensation region with a low average net dopant concentration to control capacitance
Data Source
AI summary
An electronic device can include doped regions and a trench disposed between the doped regions, wherein the trench can include a conductive member. In an embodiment, a parasitic transistor can include doped regions as drain/source regions and the conductive member as a gate electrode. A semiconductor material can lie along a bottom or sidewall of the trench and be a channel region of the parasitic transistor. The voltage on the gate electrode or the dopant concentration can be selected so that the channel region does not reach inversion during the normal operation of the electronic device.