IGZO Array Substrate Gate Layer Broken Lines for Early Conductorization Detection

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Solution Overview

Problem

The instability of the conductorizing process for indium gallium zinc oxide (IGZO) in OLED TV technology leads to poor conductorization, which can only be detected after all processes are completed, resulting in wasted resources and decreased product pass rates.

Innovation Solution

An array substrate with a gate layer having broken lines and through holes is used, allowing for early detection of IGZO conductorization by connecting the IGZO film layer in series with the gate layer, enabling identification of successful conductorization before proceeding with subsequent processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If indium gallium zinc oxide is used to form thin film transistors, then the aperture ratio is increased and image quality is improved, but the conductorizing process becomes unstable leading to poor conductorization

Engineering Contradiction:
Improveaperture ratioVSAvoidconductorizing process stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces a preliminary detection mechanism by forming a test circuit that includes the IGZO film layer, source electrode, drain electrode, and gate electrode before completing all manufacturing processes. This allows early identification of poor conductorization, enabling preliminary action to be taken before resources are wasted on defective products.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If conventional testing methods are used, then all processes must be completed before testing, but this causes waste of manpower and physical resources

Engineering Contradiction:
Improvedetection capabilityVSAvoidwaste of resources
Core Design Contradiction:
Measurement precisionVSLoss of substance

Solution Approach 1:

The patent enables preliminary testing by forming a complete test circuit structure (including source electrode, drain electrode, gate electrode, and insulating layers) that allows measurement of IGZO conductorization before final product completion. This preliminary action prevents waste of subsequent manufacturing resources on defective items.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the testing function from the final product testing stage and implements it as an integrated test circuit within the array substrate structure itself. The test circuit includes dedicated source electrode, drain electrode, and gate electrode configurations that enable independent measurement of IGZO conductorization properties.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If all processes are completed before testing, then comprehensive evaluation is possible, but the product pass rate decreases

Engineering Contradiction:
Improveevaluation completenessVSAvoidproduct pass rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary evaluation of IGZO conductorization through an integrated test circuit that can measure electrical properties before completing all manufacturing processes. This preliminary action maintains evaluation reliability while improving productivity by identifying and eliminating defective products earlier in the manufacturing sequence.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11114469B2Array substrate and fabricating method thereof, display panel and display device
Publication Date: 2021.09.07 BOE TECHNOLOGY GROUP CO LTD
  • US11114469B2 patent drawing
  • US11114469B2 patent drawing

AI summary

The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.