III-Nitride FET Gate Insulator Stack for High Breakdown Voltage
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Solution Overview
Problem
The incompatibility between MOCVD AlN gate insulators and PECVD SiN passivation dielectrics in III-nitride transistors leads to processing issues, such as degradation of the SiN film during MOCVD AlN formation, which complicates achieving low leakage current and high breakdown voltage while maintaining low on-resistance in normally-off high-power applications.
Innovation Solution
A field-effect transistor structure is developed with a dielectric layer stack that includes a MOCVD SiN gate insulator and a PECVD SiN passivation dielectric, where the gate insulator stack consists of single-crystalline AlN and polycrystalline AlN layers, and a PECVD SiN passivation layer is used to mitigate trapping effects and ensure compatibility, with a gate electrode filling a trench structure to minimize on-resistance and maximize breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOCVD AlN is used as gate insulator and PECVD SiN as passivation dielectric, then low leakage current and high breakdown voltage are achieved, but processing compatibility is compromised due to degradation of PECVD SiN film during MOCVD AlN formation
Solution Approach 1:
The gate insulator structure is segmented into multiple layers: a first AlN layer deposited by MOCVD provides high breakdown voltage, while a second AlN layer deposited by PECVD serves as a protective interface layer that prevents degradation of the PECVD SiN passivation film. This segmentation allows each layer to perform its specific function without compromising the other materials.
Solution Approach 2:
The PECVD-deposited AlN layer acts as an intermediary between the MOCVD AlN gate insulator and the PECVD SiN passivation dielectric. This intermediate layer prevents the harmful interaction between MOCVD processing and PECVD SiN, while still allowing the MOCVD AlN to provide its high breakdown voltage functionality.
2Reliability
If normally-off mode operation is implemented in III-nitride transistors, then high-power applications are enabled, but on-resistance increases and output-current decreases
Solution Approach 1:
The patent employs selective doping of the AlGaN barrier layer to create a high electron mobility channel while maintaining a high threshold voltage for normally-off operation. By carefully controlling doping parameters in specific regions, the patent achieves low on-resistance despite the normally-off mode requirement.
Solution Approach 2:
The patent uses a composite structure of AlGaN barrier layer with controlled doping combined with undoped GaN channel layer. This composite material approach enables simultaneous achievement of high electron mobility for low on-resistance and high threshold voltage for normally-off operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low gate leakage, high mobility electron channels, and maintains low on-resistance with a breakdown voltage greater than 600 volts, effectively addressing the processing incompatibility and performance requirements for high-power applications.
Implementation Method 1
metal organic chemical vapor deposition (MOCVD) AlN is a known good gate insulator material
Implementation Method 2
plasma-enhanced chemical vapor deposition (PECVD) SiN film is a known good passivation material
Data Source
AI summary
A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.