III-Nitride Metallization Cavities for Lower RF Parasitic Capacitance
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Solution Overview
Problem
Current Group III nitride RF power devices face challenges in achieving fast switching times due to high device terminal and inter-metallization capacitances, which affect their performance and energy efficiency.
Innovation Solution
A Group III nitride-based semiconductor device with a multilayer structure incorporating a metallization structure that includes electrically insulating layers and conductive redistribution structures, featuring cavities or voids to reduce capacitance, specifically designed to minimize parasitic fringing capacitances by using tungsten and copper for conductive layers and vias, and dielectric materials like silicon oxide or nitride.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional metallization structures with continuous dielectric layers are used, then device fabrication is simplified, but device terminal and inter-metallization capacitances are high
Solution Approach 1:
The patent extracts and removes portions of the dielectric material from the metallization structure to create cavities. This extraction reduces the dielectric volume between conductive elements, thereby reducing parasitic fringing capacitances while maintaining the overall metallization structure and fabrication process
Solution Approach 2:
The patent introduces a porous or cavity-containing dielectric structure within the metallization. By creating voids or cavities in the dielectric material between metal lines, the effective dielectric constant is reduced, which lowers parasitic capacitance while maintaining structural integrity
2Power
If larger metallization structures are used to carry high currents, then current carrying capacity is improved, but inter-metallization capacitances increase
Solution Approach 1:
The patent applies local quality by creating cavities specifically in regions where fringing electric fields are strongest (between adjacent metal lines), while maintaining continuous dielectric coverage where needed for current carrying. This localized modification reduces capacitance without compromising power handling
3Object-generated harmful factors
If dielectric material is removed to reduce capacitance, then parasitic fringing capacitances are reduced, but device complexity increases
Solution Approach 1:
The patent incorporates cavity formation into the preliminary metallization fabrication process. The dielectric material is removed and cavities are created during the same processing steps used to form the metallization structure, so the low-k dielectric environment is established before final device assembly, avoiding additional complex processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces drain-source, gate-drain, and gate-source capacitances, enhancing the high-frequency performance and energy efficiency of RF Power III-N Transistors by creating a low-k dielectric environment within the metallization structure, thereby improving switching times and device performance.
Implementation Method 1
The content of the cavity, e.g. the gas or vacuum and consequently the cavity has a dielectric constant that is lower than a dielectric constant of the electrically insulating layer
Data Source
Figure 1
Figure 2A~2B
Figure 2C
AI summary
In an embodiment, a Group III nitride-based semiconductor device comprises a multilayer Group III nitride-based structure comprising a first major surface; a source electrode, a gate electrode and a drain electrode arranged on the first major surface, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode and a metallization structure arranged on the first major surface. The metallization structure comprises an electrically insulating layer arranged on the source electrode, the gate electrode and the drain electrode and a conductive redistribution structure electrically connected to the source electrode, the gate electrode and the drain electrode. One or more cavities are located in the electrically insulating layer of the metallization structure.