III-V Channel 3D NAND Interface Quality
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Solution Overview
Problem
Incorporating III-V channels into 3D memory with vertical NAND strings poses challenges such as providing a good interface between the III-V channel and tunnel dielectric, achieving high electron mobility, and forming cost-effective fabrication techniques that result in high-quality NAND channels with low defects and leakage.
Innovation Solution
The use of a III-V compound channel with a mono-crystalline structure, specifically InGaAs, and a tunnel dielectric of aluminum oxide (Al2O3) to enhance interface quality and mobility, along with growth techniques like self-directed epitaxial growth to form III-V NAND channels in memory holes, and forming a metal-III-V alloy at the drain end for good Ohmic contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon channels are used in 3D vertical NAND strings, then fabrication is simpler and cost-effective, but electron mobility is limited and performance is constrained
Solution Approach 1:
The patent changes the material parameter from silicon to III-V compound semiconductors (InGaAs, InAlAs, GaAs, GaSb, InP) to achieve higher electron mobility and hole mobility, directly addressing the performance limitation of conventional silicon channels while maintaining the vertical NAND string structure
Solution Approach 2:
The patent employs composite material structures including metal-III-V semiconductor alloys at the drain end for Ohmic contact, and interfaces III-V channels with tunnel dielectrics (Al2O3, HfO2, SiO2) and charge trapping layers (SiN, AlN) to resolve interface quality issues while achieving high electron mobility
2Productivity
If III-V compound channels are used to achieve high electron mobility, then read-write efficiency improves, but interface quality between channel and tunnel dielectric becomes challenging
Solution Approach 1:
The patent introduces aluminum oxide (Al2O3) as an intermediary tunnel dielectric layer that forms a high-quality interface with III-V compound channels, and uses charge trapping layers (SiN, AlN) as intermediate structures between the channel and blocking dielectric, resolving the interface quality challenge
Solution Approach 2:
The patent replaces conventional silicon-based interfaces with III-V compound semiconductor interfaces combined with high-k dielectric tunnel barriers, substituting the traditional silicon-tunnel dielectric interface system with a new material system that achieves both high electron mobility and good interface quality
3Quantity of substance
If higher density storage is implemented using 3D stacked structure, then storage capacity increases, but chip size and program disturb increase
Solution Approach 1:
The patent applies local quality by implementing selective area epitaxial growth to form III-V compound channels only in specific memory hole regions, and uses localized charge trapping layers and tunnel dielectric structures to confine electric fields, reducing program disturb to adjacent cells while maintaining high storage capacity
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D vertical stacked architecture with vertical NAND strings extending through multiple tiers, increasing storage capacity by utilizing the third dimension while maintaining compact chip footprint and reducing program disturb through vertical isolation
4Ease of manufacture
If conventional fabrication techniques are used, then manufacturing is cost-effective, but defect density in NAND channels increases
Solution Approach 1:
The patent employs self-directed epitaxial growth where the memory hole structure itself guides the growth of III-V compound semiconductor nanowires, and uses catalyst-free vapor-liquid-solid growth mechanisms, enabling cost-effective fabrication while achieving low defect density through self-organization and minimal external intervention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high electron mobility, low sub-threshold slope, and reduced select transistor leakage, leading to improved read-write efficiency and simplified chip design with reduced program disturb and chip size.
Implementation Method 1
The III-V compound provides for high electron mobility transistor cells (as well as high hole mobility)
Implementation Method 2
a tunnel dielectric of aluminum oxide (Al2O3) to enhance interface quality and mobility
Implementation Method 3
growth techniques like self-directed epitaxial growth to form III-V NAND channels in memory holes
Implementation Method 4
forming a metal-III-V alloy at the drain end for good Ohmic contact
Data Source
AI summary
Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.