III-V E-FET Barrier Layer Split for Balanced p- and n-Channel Integration
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Solution Overview
Problem
Integrated high electron mobility transistor (HEMT) devices face performance reduction due to shared III-V layers with contradicting thicknesses and material concentrations for n-channel and p-channel devices on the same substrate, affecting the formation of two-dimensional electron gas (2DEG) and hole gas (2DHG), leading to suboptimal performance and increased cost.
Innovation Solution
The solution involves forming separate III-V layers with optimized thicknesses and material concentrations for n-channel and p-channel devices, where a thinner first barrier layer facilitates 2DEG formation and a thicker second barrier layer enhances 2DHG density, preventing leakage and improving ohmic contact, thereby increasing the performance of both devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single shared III-V barrier layer is used for both n-channel and p-channel devices, then device integration is simplified and manufacturing cost is reduced, but device performance deteriorates due to contradicting thickness requirements for optimal 2DEG and 2DHG formation
Solution Approach 1:
The patent divides the previously shared barrier layer into separate barrier layers: a first barrier layer for the n-channel device and a second barrier layer for the p-channel device. This segmentation allows each barrier layer to be independently optimized with different thicknesses and material compositions, resolving the performance contradiction while maintaining manufacturing efficiency through concurrent formation processes.
Solution Approach 2:
The patent applies local quality by providing different barrier layer characteristics in different device regions. The first barrier layer has optimized thickness and composition for n-channel device performance, while the second barrier layer has different optimized parameters for p-channel device performance. This localized optimization ensures each device type achieves its optimal performance without compromising the other.
2Reliability
If separate III-V layers with optimized thicknesses are formed for n-channel and p-channel devices, then device performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
While segmenting the barrier layer into separate first and second barrier layers increases structural complexity, the patent mitigates manufacturing complexity by enabling concurrent formation of the doped layers. This approach allows the separated structure to be fabricated using integrated processes, balancing the performance benefits against the manufacturing complexity increase.
Solution Approach 2:
The patent combines the formation of multiple doped layers in a concurrent process, merging what would otherwise be separate manufacturing steps. This merging approach reduces the overall manufacturing complexity and cost increase that would result from forming separate III-V layers with different thicknesses, while still achieving the performance improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach optimizes the performance of both n-channel and p-channel devices by ensuring optimal thickness and concentration of III-V layers, enhancing 2DEG and 2DHG formation, and reducing cost by concurrent formation of doped layers, leading to improved switching speeds and reduced sheet resistivity.
Implementation Method 1
a thinner first barrier layer facilitates 2DEG formation
Implementation Method 2
a thicker second barrier layer enhances 2DHG density, preventing leakage
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.