III-V Interconnects with Patterned Dielectric for Adhesion
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Solution Overview
Problem
Current methods for fabricating integrated circuits with III-V semiconductor devices and CMOS devices face challenges such as poor adhesion of metal layers and high costs due to time-consuming processes, particularly in forming reliable electrical interconnects between GaN devices and CMOS devices using layer transfer techniques.
Innovation Solution
The method involves forming a conductive layer over a semiconductor substrate with dielectric material areas to create a patterned lower surface for direct contact with the III-V device and a non-patterned upper surface for connection to the CMOS device, using a reduced amount of conductive material like tungsten to reduce mechanical stress and costs, and enhancing adhesion through dielectric material areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If layer transfer techniques are used to physically couple GaN and CMOS devices, then integration is achieved, but poor adhesion of metal layers occurs
Solution Approach 1:
The patent segments the metal interconnect structure into multiple layers (first metal layer, second metal layer, third metal layer) with distinct functions. The first metal layer provides adhesion to the GaN device, the second metal layer provides structural support and electrical connection, and the third metal layer provides final electrical connection to CMOS. This segmentation allows each layer to be optimized for its specific function, resolving the adhesion problem while maintaining integration capability.
Solution Approach 2:
The patent employs composite material structures in the interconnect system, combining different metal materials with complementary properties. The use of tungsten (high mechanical strength, low stress), copper (high electrical conductivity), and aluminum (good adhesion, cost-effective) creates a composite interconnect system that simultaneously achieves strong adhesion, reliable electrical connection, and mechanical stability.
2Reliability
If conventional interconnect methods are used, then electrical connections are formed, but the process is time-consuming and expensive
Solution Approach 1:
The patent performs preliminary actions by forming the complete multi-layer metal interconnect structure on the GaN device before the layer transfer process. The adhesion layer, structural metal layer, and electrical connection layers are all deposited and patterned in advance, so that when the GaN device is transferred to the CMOS substrate, the interconnect structure is already in place and ready for immediate electrical connection, eliminating time-consuming post-transfer interconnect formation steps.
Solution Approach 2:
The patent merges multiple fabrication steps into a unified process flow. The interconnect structure formation is combined with the layer transfer process itself, allowing simultaneous achievement of device transfer and interconnect formation. This integration of processes reduces the total number of fabrication steps, decreases manufacturing time, and lowers costs while maintaining connection reliability.
3Reliability
If multiple levels of dielectric and metal interconnection layers are used, then electrical interconnects are formed, but mechanical stress and peeling issues occur
Solution Approach 1:
The patent changes the material parameters of the interconnect layers to optimize mechanical properties. By selecting tungsten for the structural layer (low stress, high strength), copper for electrical conductivity (low resistivity), and aluminum for adhesion (good bonding), the patent achieves a balance where the interconnect structure provides reliable electrical connection without introducing excessive mechanical stress that would cause peeling or deformation.
Solution Approach 2:
The patent introduces an adhesion layer as an intermediary between the GaN device and the metal interconnect structure. This adhesion layer acts as a mediator that bonds to both the GaN surface and the metal layers, distributing mechanical stresses and preventing direct stress concentration at the GaN-metal interface, thereby eliminating peeling issues while maintaining interconnect reliability.
4Ease of manufacture
If GaN devices are formed on silicon (111) substrates, then epitaxial growth is achieved, but interface traps are created
Solution Approach 1:
The patent extracts the problematic silicon (111) substrate interface by transferring the GaN device to a different substrate platform. The layer transfer technique allows the GaN device to be separated from its original silicon substrate and repositioned on a CMOS-compatible substrate, thereby removing the source of interface traps while preserving the epitaxially grown GaN device structure and its manufacturing advantages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces mechanical stress and peeling issues, improves adhesion, and decreases the cost of interconnect material deposition, while ensuring reliable electrical connections between III-V and CMOS devices, even with imperfect alignment.
Implementation Method 1
The first interconnect material, which may include tungsten, may reduce mechanical stress
Implementation Method 2
enhancing adhesion through dielectric material areas
Implementation Method 3
forming a first conductive layer over the semiconductor substrate and in electrical contact with the first device
Implementation Method 4
depositing a first interconnect metal over the plurality of dielectric material areas and over the uncovered portions of the upper surface of the first conductive layer
Data Source
AI summary
Integrated circuits, methods for fabricating integrated circuits, and methods for fabricating electrical interconnects for III-V devices are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a III-V device over and/or within a semiconductor substrate. The method further includes forming a conductive layer over the semiconductor substrate and electrically connected to the device. The conductive layer has an upper surface. Also, the method includes forming a plurality of dielectric material areas over the upper surface of the conductive layer to define covered portions and uncovered portions of the upper surface of the conductive layer. The method includes depositing an interconnect metal over the plurality of dielectric material areas and over the uncovered portions of the upper surface of the conductive layer. The interconnect metal is electrically connected to the upper surface of the conductive layer.