Solid-state Image Pickup Device with Offset Wiring Layout
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Solution Overview
Problem
The parasitic capacity between vertical signal lines in solid-state image pickup devices hinders the promotion of high-frame rates, as it affects the stability and efficiency of signal readout.
Innovation Solution
A solid-state image pickup device with a pixel array configuration that includes a substrate with shared photoelectric conversion regions, multiple layers with offset wirings, and vias connecting signal lines to these wirings, which reduces parasitic capacity by optimizing the layout and arrangement of connection wirings and signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple vertical signal lines are provided per pixel column to enable high-speed readout, then readout speed is improved, but parasitic capacity between signal lines increases which hinders high-frame rate promotion
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked wiring with multiple layers (first layer, second layer, third layer) and vertical vias. This dimensional change allows signal lines to be routed through different spatial levels, reducing parasitic capacity between adjacent lines while maintaining high readout speed capability
Solution Approach 2:
The patent segments the pixel circuit into multiple functional blocks distributed across different layers: photoelectric conversion regions in the substrate, pixel circuits in the first layer, and signal line connections through vias to upper layers. This segmentation reduces inter-layer parasitic capacity while preserving readout performance
2Productivity
If pixel circuits are configured with multiple transfer elements and multi-layer wiring to improve signal output, then signal readout efficiency is improved, but device complexity increases
Solution Approach 1:
The patent employs transfer elements (first transfer elements and second transfer elements) that serve multiple functions: charge transfer from photoelectric conversion regions, signal routing between layers, and capacity balancing across different pixel units. This multi-functionality improves readout efficiency without proportionally increasing complexity
Solution Approach 2:
The patent implements a nested hierarchical structure where pixel circuits are embedded in the first layer, signal lines are routed through the second layer, and vertical connections are established via vias to the third layer. This nested arrangement organizes complexity systematically while enabling efficient signal readout
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the parasitic capacity of vertical signal lines, enabling higher frame rates and improved signal readout efficiency by reducing the time constant and settling time of pixel signals.
Implementation Method 1
a substrate including a first photoelectric conversion region and a second photoelectric conversion region
Data Source
Figure 1
Figure 2A~2C
Figure 3
AI summary
An imaging device includes a pixel array including a plurality of pixel units in a matrix arrangement. At least a first pixel unit of the plurality of pixel units includes a substrate including a first photoelectric conversion region and a second photoelectric conversion region, and a first layer over the substrate and including a first pixel circuit and a second pixel circuit. The first pixel unit includes a second layer over the first layer and including first and second wirings extending in a first direction, and a third layer over the second layer and including signal lines that extend in the second direction. The first pixel unit includes a first via that couples a first signal line to the first wiring, and a second via offset from the first via in the first direction and that couples a second signal line to the second wiring.