Image Processing Apparatus Allowance Signal Coordination

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Solution Overview

Problem

Existing image processing apparatuses face challenges in maintaining transfer performance and preventing abnormal image data generation when functional expansion is implemented, as the output timing of allowance signals needs to be adjusted based on varying image processing times and communication rates, but no method has been proposed to address this effectively.

Innovation Solution

The image processing apparatus includes a first memory, a memory controller, a first image processor, a second image processor, a connector, a first generator for generating an allowance signal based on the first image processor's processing time, a second generator for the second image processor's processing time, and an allower that synthesizes these signals to determine the optimal timing for reading the next line of image data from memory, ensuring that image processing is not interrupted during data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If functional expansion is implemented by adding a second image processor, then image processing capability is improved, but the timing coordination of allowance signals becomes complex and may cause abnormal image data

Engineering Contradiction:
Improveimage processing capabilityVSAvoidtiming coordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

An allower unit is introduced as an intermediary component that receives allowance signals from both the first generator (for the first image processor) and the second generator (for the second image processor). The allower synthesizes these signals and outputs a coordinated allowance signal to the memory controller, thereby managing the timing complexity introduced by functional expansion without affecting the image processing capability of individual processors.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If allowance signal timing is adjusted based on varying image processing times, then image processing continuity is maintained, but transfer performance may be degraded due to conservative timing

Engineering Contradiction:
Improveimage processing continuityVSAvoiddata transfer performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts allowance signal timing based on the actual processing speeds of the first and second image processors. The first generator and second generator independently determine allowance signal timing according to their respective processing times, and the allower coordinates these dynamic timings. This dynamic adaptation maintains image processing continuity while optimizing data transfer performance by avoiding unnecessarily conservative timing.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If a single allowance signal is used for one image processor, then the system is simple, but functional expansion to multiple processors cannot be supported

Engineering Contradiction:
Improvefunctional expansion capabilityVSAvoidsignal generation structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The allowance signal generation function is segmented into multiple independent generators: a first generator for the first image processor and a second generator for the second image processor. Each generator independently manages timing for its associated processor based on processing time. This segmentation enables functional expansion to multiple processors while maintaining manageable complexity through the coordinating allower unit.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10798262B2Image processing apparatus, image processing apparatus controlling method, and recording medium
Publication Date: 2020.10.06 RICOH CO LTD
  • US10798262B2 patent drawing
  • US10798262B2 patent drawing
  • US10798262B2 patent drawing

AI summary

An image processing apparatus includes a memory holding image data generated by an image reader; a memory controller for accessing the memory; first and second image processors for executing image processing on the image data one line at a time, the second image processor being added when implementing functional expansion; a connector for connecting the first and second image processors by a transfer path of the image data when implementing the functional expansion; first and second generators for respectively generating first and second allowance signals for allowing reading of a next line of the image data from the memory, according to the image processing times taken by the first and second image processors; and an allower configured to output, to the memory controller, a third allowance signal for allowing reading of the next line of the image data from the memory, based on the first and second allowance signals.