Energy Efficient Computing TRIZ Cases

A shared Ethernet NIC scheme using independent PCIe uplinks and Virtual Ethernet Bridging switches to enable efficient data transfer across multiple processor subsystems.

Independent pair sampling circuit detects earliest signal transitions to generate clock pulses, accommodating wire timing skews in multi-wire interfaces.

Segmenting the PCIe switch architecture reduces operational power consumption and manufacturing costs by eliminating unnecessary crossbar routing.

Queue-based gear shifting minimizes frequency of gear shifts, reducing power consumption in UFS systems.

A merged super network combines a pretrained backbone with a target detection rear end to enable Neural Architecture Search.

Controller switches direct and memory copy modes based on key presses to manage shading correction data acquisition.

Network interface enables remote input operations while touch panel switches to local mode.

A printing controller switches modes to store and cut data from multiple external devices.

A voltage regulator switch enables remote bus wake-up for master transceivers, eliminating extra wiring and reducing power consumption.

An I/O channel abstraction system establishes logical communication paths between accelerator device kernels.

A human interface device stores monitor settings as binary data for cross-device portability.

A network interface device selects hardware resources based on data processing measurements and power states.

A mentor layer manages variables in local high-speed memory frames and bins, overcoming namespace complexity while enhancing parallelism.

Image formation apparatus moves files from shared hot folders to private storage upon detection.

External peripheral component bus cables connect multiple hosts to one network interface controller, reducing hardware duplication and thermal output.

A content addressable memory module determines next best DRAM access requests using parallel hardware search operations.

A determination unit assesses setting information across multiple image data pieces on a single page to identify common parameters.

A controller adjusts job queue order to prioritize non-parallelizable tasks within an image forming apparatus.

An annular capacitor design segments the preparation process from the gate layer, reducing etching complexity and improving yield in 3D memory stacks.

A control method identifies differences in print settings before and after switching image output apparatuses to automate configuration handling.

Shielding layer between touch and data signal lines prevents electromagnetic interference, maintaining touch accuracy without adding manufacturing complexity.

Endpoint specific switching decision logic schedules data access via pre-fetch DMA descriptors to eliminate host processor waiting time.

Cloud data recovery service transmits change streams from storage systems to meet specific RTO and RPO targets.

Interrupts printing upon error detection to notify external devices of interrupted recording media, enabling accurate management of incomplete prints.

An information processing apparatus manages network connectivity and service registration for image devices.

Dynamic transfer speed adjustment prevents data congestion during parallel scan and print operations, maintaining high scanning efficiency.

A USB hub device uses a multi-mode physical layer to manage differential signal transmission across upstream and downstream ports.

A printing system pauses image formation upon receiving a cancellation instruction to allow vocal user identification of the target job.

A Bluetooth Low Energy control method caches Generic Attribute Profile structure data to expedite subsequent device connections.

A peripheral virtualization controller manages I/O device registers and command parsing to enable seamless switching between multiple host processors.

A network interface analyzes reception packets to control printer engine power supply states.