3D 1S1C Memory Ring Capacitor Etching Process
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Solution Overview
Problem
Current 3D-1S1C memory technologies face challenges in simplifying the complex preparation processes of capacitors, particularly in 3D-NAND-like structures, which result in reduced yield and increased complexity.
Innovation Solution
A three-dimensional 1S1C memory based on a ring capacitor is proposed, featuring a horizontal peripheral electrode layer, a vertical functional layer, and a capacitive dielectric layer. The capacitor preparation process is simplified by using an annular capacitor design that is etched separately from the gate layer, reducing the number of etching steps and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a structure similar to floating gate 3D-NAND is adopted, then multi-layer memory stacking is easier to implement, but the preparation process of capacitors becomes more complicated requiring multiple etching processes
Solution Approach 1:
The patent segments the capacitor preparation from the gate layer preparation by introducing an annular capacitor structure that is etched separately. The annular groove is etched first to form the capacitor region, then the gate layer is formed in the remaining areas. This segmentation allows independent optimization of each component's fabrication process.
Solution Approach 2:
The patent extracts the capacitor formation process from the conventional integrated gate-capacitor approach. By taking out the capacitor region as a separate annular structure surrounding the gate, the capacitor can be prepared independently with simplified etching, avoiding the complex multi-step etching required in traditional 3D-NAND capacitor fabrication.
2Reliability
If multiple independent horizontal capacitors are prepared in deep holes, then memory function is achieved, but the number of etching processes increases reducing yield
Solution Approach 1:
The patent transitions from horizontal capacitors in deep holes to a vertical annular capacitor structure. The capacitor is formed as an annular groove surrounding the vertical gate, with the capacitive dielectric layer filling the annular space. This dimensional change from horizontal to vertical configuration reduces the number of etching steps while maintaining memory functionality.
Solution Approach 2:
The patent merges the capacitor structure with the gate structure by positioning the annular capacitor groove around the gate. The same etching process that defines the gate also defines the capacitor region, and the capacitive dielectric layer is deposited in the annular space, combining what would traditionally be separate fabrication sequences.
Data Source
AI summary
The invention discloses a three-dimensional 1S1C memory based on a ring capacitor and a preparation method. The memory includes: a horizontal peripheral electrode layer including a first dielectric layer and a first metal electrode layer alternately stacked and grown on a substrate and provided with trenches penetrating in a vertical direction and holes penetrating in the vertical direction, a vertical functional layer, and a capacitive dielectric layer. An annular groove is disposed outside each hole. The annular groove surrounds the holes and vertically cuts off the peripheral electrode layer. The annular groove is evenly filled with a capacitive dielectric layer. A top of the second metal electrode layer is extended to a surface of a topmost first dielectric layer to form a bit line electrode and is connected to a bit line. A region where the second metal electrode layer faces the first metal electrode layer forms a memory cell.