Processor Frames Bins Local Memory Mentor Layer
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Solution Overview
Problem
Current computer processor architectures face limitations in exploiting increased transistor counts due to the 'ILP Wall' and 'Memory Wall,' primarily due to namespace management issues in register machines, which hinder parallelism and efficiency, especially in handling shared variables and memory access.
Innovation Solution
The introduction of a multi-layer control structure with a mentor layer and instruction/control layer, where the mentor layer manages variables in local high-speed memory and associated caches, communication channels, and instrumentation devices, enabling efficient operand access and parallel operations by mapping logical variables to physical memory locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If register architecture namespace management is used to manage variables, then processor performance can be improved through fast access, but the namespace mechanism interferes with parallelism and creates complexity
Solution Approach 1:
The patent segments the namespace management function by introducing a separate mentor layer that handles variable management independently from the instruction execution layer. This segmentation allows the register architecture to maintain fast variable access while the mentor layer handles the complexity of namespace management, parallelism coordination, and memory access control, thus resolving the contradiction between speed and complexity.
2Productivity
If multiple copies of functional units are added to increase performance, then more operations can be performed in parallel, but shadow register structures become overly complex
Solution Approach 1:
The patent introduces the mentor layer as an intermediary between the functional units and the register architecture. This mentor layer manages variable access and coordinate parallel operations without requiring complex shadow register structures. The mentor circuits handle the coordination of multiple functional units and manage variable state, thereby enabling high productivity while keeping the register structure simple.
3Speed
If cache memory is introduced to solve operand access delays, then access speed improves, but coherency issues arise when program changes operand values
Solution Approach 1:
The patent implements feedback mechanisms in the mentor layer that monitor and track variable access and modifications. The mentor circuits receive information about program changes to operand values and can coordinate with cache memory to maintain coherency. This feedback approach allows the system to maintain fast cache access while ensuring variable coherency through active monitoring and coordination.
4Quantity of substance
If larger memory is accessed to handle bigger systems, then more data can be processed, but the speed of clock cycle and pin to pin interconnect are limited
Solution Approach 1:
The patent addresses the memory speed limitation by organizing memory access through the mentor layer which manages variables and can optimize access patterns. The mentor circuits can coordinate access to larger memory capacities while maintaining efficient data flow to functional units. This dimensional approach to memory management allows the system to access larger memory capacities without being bottlenecked by physical interconnect speeds.
Data Source
AI summary
A computing device includes a main memory; a local high speed memory; one or more functional units, one or more interconnects between the main memory and the local high speed memory, and one or more interconnects between the local high speed memory and the one or more functional units. The local high speed memory implements a frames/bins structure. The local high speed memory includes a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames. Each of the bins includes a logical element. The functional units perform operations relating to Variables stored in the bins, each of the Variables including one or more words.