Independent 3-Phase Eye Sampling Circuit for C-PHY Clock Recovery
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Solution Overview
Problem
Current clock generation circuits in multi-wire, multi-phase data communication links, such as the C-PHY interface, face limitations in speed and efficiency due to variations in signal transition times and timing skews between wires, which affect the ability to recover clock information accurately.
Innovation Solution
The proposed solution involves a method and apparatus for clock and data recovery that utilize difference signals from pairs of wires to generate a clock signal by detecting the earliest-occurring transition between symbols, using edge-triggered flipflops to determine the direction of voltage change and selecting values based on these transitions, allowing for improved clock recovery even when transitions occur at different times on different wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If common timing is used for capturing signaling state on all conductors, then timing synchronization is simplified, but the transmission rate is limited due to maximum time variation among conductors
Solution Approach 1:
The patent divides the clock recovery process into separate independent paths for each difference signal (AB, BC, CA). Each difference signal has its own eye opening detection and sampling circuit, allowing independent optimization without being constrained by the maximum time variation across all conductors. This segmentation enables higher transmission rates while maintaining timing synchronization through separate recovery circuits for each signal pair.
2Measurement precision
If delay circuits are employed to ensure stable signaling state before sampling, then sampling accuracy is improved, but the transmission rate is limited by the delay time required
Solution Approach 1:
The patent dynamically adapts the sampling timing to each individual difference signal's eye opening characteristics. Instead of using fixed delay circuits that impose a uniform sampling time on all signals, the system detects the actual eye opening for each difference signal and adjusts the sampling point accordingly. This dynamic approach maintains sampling accuracy while minimizing the time penalty, thereby enabling higher transmission rates.
3Stability of the object's composition
If the maximum time variation among conductors is used to determine sampling timing, then all conductors are synchronized, but the transmission rate is limited by the slowest conductor
Solution Approach 1:
The patent applies local quality optimization by treating each difference signal (AB, BC, CA) individually with its own eye opening detection and sampling timing. Rather than imposing a uniform timing constraint based on the maximum variation across all conductors, each signal pair receives customized sampling parameters optimized for its specific characteristics. This allows faster-conducting pairs to operate at higher rates without being held back by slower pairs.
Data Source
AI summary
Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol.