Image Sensor Device Stacking ADC Array via Interlayer Vias
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Solution Overview
Problem
Existing image sensor devices face challenges in miniaturization and cost due to difficulties in electrically connecting separate CMOS image sensor and peripheral logic circuit chips, with limitations in connection pitch and high costs associated with bonding techniques like microbumps and TSVs.
Innovation Solution
The solution involves stacking a CMOS image sensor device with an ADC array formed using SiGeSn transistors on a semiconductor substrate, connecting them via interlayer vias without microbumps or TSVs, allowing for high-density and accurate electrical connections within a CMOS manufacturing process, enabling compatibility with small-sized CISs and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate chips are bonded using microbumps or TSVs to connect pixel portion and peripheral logic circuit, then electrical connection between chips is achieved, but connection pitch is limited to 5 μm or more and manufacturing costs increase
Solution Approach 1:
The patent merges the pixel portion and peripheral logic circuit onto a single semiconductor substrate, eliminating the need for separate chip bonding. This integration allows interlayer vias to directly connect the two functional regions without requiring microbumps or TSVs, thereby achieving connection pitches smaller than 5 μm and reducing manufacturing costs.
Solution Approach 2:
The patent segments the semiconductor substrate into distinct functional regions: a pixel portion region and a peripheral logic circuit region. These regions are formed on the same substrate at different locations, allowing high-density interlayer via connections without the constraints of separate chip bonding technologies.
2Reliability
If separate chips are bonded using microbumps or TSVs to connect pixel portion and peripheral logic circuit, then electrical connection is achieved, but manufacturing costs increase due to thinning, dicing, alignment, and bonding processes
Solution Approach 1:
The patent combines the pixel portion and peripheral logic circuit fabrication into a single CMOS manufacturing process on one substrate. This eliminates multiple costly processes including separate chip thinning, dicing, alignment, and bonding operations, thereby significantly reducing manufacturing costs while maintaining reliable electrical connections through interlayer vias.
3Area of stationary object
If ADCs are placed on the sides of pixels in conventional column parallel system, then chip area increases, but if stacked separately then connection pitch cannot be minimized
Solution Approach 1:
The patent transitions from a planar arrangement where ADCs are placed on the sides of pixels to a vertical stacking arrangement using interlayer vias. This dimensional change allows ADCs to be positioned in the third dimension (vertical layer) rather than consuming horizontal chip area, achieving both compact chip area and minimized connection pitch through direct vertical connections.
Data Source
AI summary
According to one embodiment, an image sensor device includes a sensor array on a semiconductor substrate, the sensor array including blocks, each of the blocks including a pixel and outputting a signal of the pixel; a first insulating layer on the sensor array; semiconductor layers on the first insulating layer; analog-digital converting circuits on the semiconductor layers, the analog-digital converting circuits corresponding to the blocks and processing the signal; a second insulating layer on the first insulating layer and the analog-digital converting circuits; and interconnect portions electrically connecting the analog-digital converting circuits to the blocks via a region between the semiconductor layers, the interconnect portions extending across the first insulating layer and the second insulating layer.