Stacked Image Sensor Covering Film Clearance for Chip-End Stress
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Solution Overview
Problem
Existing back-illuminated solid-state imaging devices face issues with tensile stress and alignment deviations due to the expansion and fixation of chips during oxide film formation, which restricts transistor placement near chip ends and affects mechanical strength.
Innovation Solution
A solid-state imaging device with a clearance or buffer film formed between the covering film and the chip, using a low-temperature film or low Young's modulus material, such as an organic film or inorganic films like SiO2, Si3N4, SiC, Cu, Al, or C, to reduce tensile stress and allow transistor placement near chip ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are heated to high temperature during oxide film formation, then the oxide film can be formed and cover the chip, but tensile stress is produced in the chip causing transistor characteristic changes and alignment deviation
Solution Approach 1:
The patent changes the formation temperature parameter from conventional high temperature to low temperature (e.g., room temperature or slightly elevated). This allows the oxide film to be formed without causing thermal expansion and subsequent tensile stress in the chip, thereby preventing transistor characteristic changes and alignment deviation while still achieving reliable oxide film coverage.
2Productivity
If the substrate thickness is reduced to achieve three-dimensional integration, then device integration and performance are improved, but mechanical strength becomes insufficient and warp is produced
Solution Approach 1:
The patent employs a composite structure combining the thinned substrate with a supporting layer or reinforcement structure. This composite approach allows the substrate to be sufficiently thin for high-density three-dimensional integration while the supporting layer provides the necessary mechanical strength to prevent warp and maintain structural integrity during manufacturing and operation.
3Reliability
If a KOZ is set from chip ends to cope with stress effects, then transistor characteristic stability is improved, but chip area is reduced and transistor circuits cannot be provided near ends
Solution Approach 1:
By changing the temperature parameter to low-temperature oxide film formation, the patent eliminates the need for KOZ regions. The low-temperature process prevents tensile stress generation, allowing transistors to be reliably placed right up to the chip edges without characteristic instability, thereby maximizing the usable chip area for transistor circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces tensile stress and allows for transistor placement near chip ends, improving mechanical strength and reducing chip size, thereby enhancing manufacturing yields and cost-effectiveness.
Implementation Method 1
a covering film that covers a non-lamination portion that is a region where the semiconductor element is not laminated, in a laminated surface of the solid-state imaging element where the semiconductor element is laminated, and further covers a peripheral side surface of the semiconductor element and forms a clearance between the peripheral side surface of the semiconductor element and the covering film
Data Source
AI summary
An object is to provide a solid-state imaging device, a manufacturing method of a solid-state imaging device, and an electronic apparatus that are capable of reducing tensile stress produced between a covering film and a semiconductor element which is joined to a solid-state imaging element and which is covered with the covering film, and that allow transistors to be provided near chip ends. There is provided a configuration including a solid-state imaging element, a semiconductor element laminated on the solid-state imaging element and electrically connected to the solid-state imaging element, and a covering film that covers a non-lamination portion that is a region where the semiconductor element is not laminated, in a laminated surface of the solid-state imaging element where the semiconductor element is laminated, and further covers a peripheral side surface of the semiconductor element and forms a clearance between the peripheral side surface of the semiconductor element and the covering film. This configuration can reduce tensile stress produced at chip ends of the semiconductor element when a covering film such as an oxide film is formed on the non-lamination portion of the solid-state imaging element and on an entire surface including the peripheral side surface of the semiconductor element on a side opposite to a lamination surface.