Image-Sensor Digital Circuit DVFS for Low-Power Motion Detection
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Solution Overview
Problem
Existing image sensors face challenges in reducing power consumption, particularly during periods of low activity, such as the V-blanking period in CMOS image sensors, without impacting performance.
Innovation Solution
Implementing dynamic voltage and frequency scaling (DVFS) within a single frame operation, where higher voltage and frequency are applied during active read periods and lower voltage and frequency during V-blanking periods to maintain functionality while minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling is implemented within a frame, then power consumption is reduced during V-blanking periods, but circuit complexity increases
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling by making the power supply voltage and clock frequency adjustable within a single frame period. The system transitions from static operating parameters to dynamic parameters that can change based on operational requirements, enabling lower voltage/frequency during V-blanking periods and higher voltage/frequency during read periods, thus resolving the contradiction between power consumption and circuit complexity
Solution Approach 2:
The patent changes the operating parameters (voltage and frequency) dynamically within the frame sequence. By modifying these parameters based on the operational state (read period vs. V-blanking period), the system achieves reduced power consumption during inactive periods while maintaining performance during active periods, addressing the technical contradiction
2Use of energy by moving object
If lower voltage and frequency are supplied during V-blanking periods, then power consumption is reduced, but data retention capability may be compromised
Solution Approach 1:
The patent applies different voltage and frequency levels to different operational phases within the same frame. During V-blanking periods, lower voltage and frequency are applied to reduce power consumption, while during read periods, higher voltage and frequency are applied to ensure proper data retention and processing. This localized optimization resolves the contradiction between power savings and data retention
Solution Approach 2:
The system performs preliminary actions by maintaining sufficient voltage and frequency during V-blanking periods to ensure data retention before the next read operation. The controller is configured to supply voltage and frequency that are sufficient for maintaining operational state, preventing data loss while minimizing power consumption during these transition periods
Data Source
AI summary
An imaging device having a digital circuit block therein subjected to in-frame DVFS during a frame sequence of the sensing operating mode. In an example embodiment, the in-frame DVFS causes a higher power-supply voltage and a higher clock frequency to be supplied to the digital circuit block during read periods of the frame sequence, and a lower power-supply voltage and a lower clock frequency to be supplied to the digital circuit block during V-blanking periods of the frame sequence. The lower power-supply voltage and clock frequency are selected to be sufficient for the digital circuit block to support the pertinent functions thereof during the V-blanking periods without adversely impacting performance. For example, the lower power-supply voltage is sufficient for a SRAM of the digital circuit block to retain data therein. Beneficially, the in-frame DVFS enables the imaging device to perform motion detection while consuming very little power.