Image Sensor FDTI Sealing Layer to Block Polysilicon Infiltration
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Solution Overview
Problem
The infiltration of polysilicon into the seams of the floating diffusion trench isolation (FDTI) oxide layer in CMOS Image Sensors (CIS) leads to performance defects and inconsistency, hindering pixel shrinkage while maintaining high image quality.
Innovation Solution
Employing selective silicon epitaxial growth (SEG) for a crystalline sealing layer to prevent polysilicon deposition in the oxide seam, combined with a dry etch process and pre-clean cycles to form a flat Si-EPI merged-plane over the thin oxide layer, enhancing the sealing layer's etching resistance and sensor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon is deposited in the oxide seam of FDTI structure, then the sealing effect is compromised, but polysilicon infiltration into the oxide seam causes performance defects and inconsistency
Solution Approach 1:
The patent removes the problematic oxide seam from the FDTI structure by using a selective etch process that eliminates the oxide layer between trenches. This extraction of the harmful oxide seam prevents polysilicon infiltration defects while maintaining the sealing function through alternative means.
Solution Approach 2:
The patent converts the potentially harmful oxide seam into a beneficial etch stop layer. By controlling the oxide layer thickness and using selective etching, the oxide seam that would normally cause polysilicon infiltration is transformed into a protective barrier that stops etching at the desired location, preventing defects.
2Productivity
If pixel size is reduced to increase functional density, then production efficiency improves, but maintaining high image quality becomes difficult due to infiltration defects
Solution Approach 1:
The patent changes the physical and chemical parameters of the oxide layer, including its thickness and composition, to create an optimized etch stop layer. By controlling these parameters, the process enables reliable pixel shrinkage while maintaining image quality consistency across different pixel sizes.
Solution Approach 2:
The patent performs preliminary preparation of the oxide layer before polysilicon deposition, creating a controlled etch stop structure in advance. This preliminary action ensures that subsequent processing steps proceed uniformly, enabling consistent image quality even as pixel dimensions are reduced for higher productivity.
3Device complexity
If conventional deposition processes are used without pre-clean cycles, then process simplicity is maintained, but layer formation accuracy deteriorates
Solution Approach 1:
The patent introduces a pre-clean cycle as a preliminary action before the main deposition process. This pre-clean step prepares the substrate surface by removing contaminants and oxides, ensuring accurate layer formation. The pre-clean cycle is integrated into the overall process in a way that maintains simplicity while dramatically improving precision.
Solution Approach 2:
The patent creates a continuous process flow where the pre-clean cycle seamlessly transitions into the deposition process. By eliminating idle time and ensuring continuous useful action from cleaning to deposition, the process maintains simplicity while achieving high layer formation accuracy through uninterrupted surface preparation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures accurate layer formation, prevents dielectric layer damage, and enhances the image sensor's performance by reducing defects and inconsistencies, allowing for pixel shrinkage without compromising image quality.
Implementation Method 1
Employing selective silicon epitaxial growth (SEG) for a crystalline sealing layer to prevent polysilicon deposition in the oxide seam
Implementation Method 2
combined with a dry etch process and pre-clean cycles to form a flat Si-EPI merged-plane over the thin oxide layer
Data Source
AI summary
A method includes forming a doped region in a substrate; forming a doped well vertically extending from a front side of the substrate into the doped region; forming a transfer gate over the front side of the substrate and laterally between a first portion of the doped well and a second portion of the doped well; forming a trench vertically extending form the front side of the substrate through the doped well toward a back side of the substrate; depositing an dielectric material over the front side of the substrate and in the trench; recessing the dielectric material; performing a selective epitaxial growth process to form a sealing layer in the trench and over the recessed dielectric material from the front side of the substrate; forming an electrode in the trench and over the sealing layer from the front side of the substrate.