Image Sensor Gate Electrode Buried Portion Design
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Solution Overview
Problem
Highly integrated semiconductor image sensors experience image lag and cross talk due to scaled-down pixels, which affect their performance in converting light into electric signals effectively.
Innovation Solution
The image sensor design includes a substrate with pixel regions, photoelectric conversion parts, and gate electrodes with buried portions having a flat bottom surface and rounded lower corner, along with a deep device isolation layer and a shallow device isolation layer, to reduce cross talk and improve light reception efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixels are scaled down for high integration, then device integration is improved, but image lag and cross talk occur more often
Solution Approach 1:
The patent introduces deep device isolation layers that completely penetrate the substrate to divide pixel regions into separate compartments. This segmentation prevents electrical signal interference (cross talk) between adjacent pixels while maintaining high integration density, and the complete isolation eliminates charge carrier diffusion paths that cause image lag.
Solution Approach 2:
The patent transitions from conventional shallow isolation methods to deep vertical isolation structures that extend through the entire substrate thickness. This dimensional change from surface-level to through-substrate isolation enables effective pixel separation in the vertical dimension, solving cross talk and image lag issues without compromising horizontal integration density.
2Area of stationary object
If pixels are scaled down for high integration, then area efficiency is improved, but light reception efficiency deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension by implementing deep isolation layers that extend through the substrate, enabling better control of the electric field distribution in the vertical direction. This improves charge carrier collection efficiency and light reception performance without increasing the horizontal pixel area, thus maintaining area efficiency while enhancing light reception.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the deep device isolation layers are positioned strategically between pixel regions to create localized electric field confinement, while the pixel regions themselves maintain optimized photodiode structures for light reception. This local differentiation enables simultaneous optimization of both area efficiency and light reception efficiency.
3Reliability
If deep device isolation layer is introduced to reduce cross talk, then pixel separation is improved, but device complexity increases
Solution Approach 1:
The patent divides the isolation function into distinct segments: deep device isolation layers for complete pixel separation and shallow device isolation layers for surface-level structure definition. This segmentation of isolation functions achieves effective cross talk reduction while organizing the complex structure into manageable, systematically arranged components that can be manufactured using standardized processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces image lag and cross talk between pixels, enhancing the image sensor's ability to convert light into electric signals and improving the fill factor by ensuring effective electric field distribution and light reception.
Implementation Method 1
Each of the pixels includes a photodiode (PD), which converts incident light into an electric signal
Implementation Method 2
The deep device isolation layer may include an insulating material, whose refractive index may be different from that of the substrate
Data Source
AI summary
Provided are image sensors and methods of fabricating the same. The image sensor has a transfer gate, which may be configured to include a buried portion having a flat bottom surface and a rounded lower corner. This structure of the buried portion enables to transfer electric charges stored in the photoelectric conversion part effectively.