Solid-State Image Sensor Gate Electrode Segmentation
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Solution Overview
Problem
Conventional solid-state image sensors face challenges in reducing the total capacitance of the floating diffusion region, which limits the detection sensitivity of output signals due to reduced capacitance between the floating diffusion region and the output gate electrode.
Innovation Solution
The design involves forming a first impurity region at a larger distance from the first gate electrode and a second gate electrode at a shorter distance from the first impurity region, reducing capacitances related to the first impurity region, thereby increasing the extracted signal voltage and improving detection sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the floating diffusion region is positioned closer to the output gate electrode to reduce distance, then the capacitance between them increases, but this increases the total capacitance of the floating diffusion region and reduces detection sensitivity
Solution Approach 1:
The patent divides the gate electrode structure into multiple segments: a first gate electrode positioned at a first distance from the floating diffusion region, and a second gate electrode positioned at a second distance from the floating diffusion region. This segmentation allows independent optimization of distances to manage capacitance while maintaining detection sensitivity. The segmented gate structure enables different regions to serve different functional purposes in capacitance control.
Solution Approach 2:
The patent introduces a vertical dimension to the gate electrode arrangement by stacking gate electrodes at different heights and positions. The first gate electrode is positioned at a first distance in one dimension while the second gate electrode is positioned at a second distance in another dimension, creating a three-dimensional capacitance management strategy that goes beyond simple planar distance reduction.
2Measurement precision
If the distance between the floating diffusion region and the gate electrode is increased to reduce capacitance, then detection sensitivity improves, but the area occupied increases and device integration becomes more difficult
Solution Approach 1:
The patent utilizes vertical stacking and three-dimensional positioning of gate electrodes to reduce the horizontal area footprint. By positioning gate electrodes at different vertical levels and distances, the design achieves effective capacitance reduction without proportionally increasing the planar device area, as the capacitance management is achieved through spatial distribution in multiple dimensions rather than simple lateral expansion.
Solution Approach 2:
The patent optimizes multiple parameters simultaneously: the first distance between the floating diffusion region and the first gate electrode, the second distance between the floating diffusion region and the second gate electrode, and the relative positioning of the gate electrodes. By carefully controlling these geometric parameters, the design achieves reduced capacitance and improved detection sensitivity while maintaining compact device dimensions suitable for integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration efficiently reduces capacitances, enhancing the voltage of the extracted signal and improving detection sensitivity for output signals by optimizing the distances between the impurity regions and gate electrodes.
Implementation Method 1
the capacitance between the floating diffusion region and the output gate electrode is reduced. An interlayer dielectric film is formed to cover the second-layer transfer gate electrodes
Implementation Method 2
The solid-state image sensor alternately applies two-phase clock pulse signals ΦH1 and ΦH2 to the respective transfer gate electrodes 105, as shown in FIG. 25. The solid-state image sensor is so formed as to transfer signal charges stored in the transfer channel region 103 to the region located under the output gate electrode 106 by vertically moving channel potentials in potential wells formed in portions of the transfer channel region 103 located under the transfer gate electrodes 105 respectively
Data Source
AI summary
A solid-state image sensor capable of improving detection sensitivity for an output signal is provided. This solid-state image sensor comprises a first gate electrode formed on a semiconductor substrate, a first impurity region formed on the semiconductor substrate at a first distance from the first gate electrode for receiving the signal charges and a second gate electrode formed at a second distance from the first impurity region for discharging unnecessary signal charges after extraction of a voltage signal from the first impurity region. The first distance between the first impurity region and the first gate electrode is larger than the second distance between the first impurity region and the second gate electrode.