Image Sensor Interconnection Layer for Reduced Chip Size
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Solution Overview
Problem
There is a demand for image sensors with increased miniaturization and resolution, and existing technologies have not adequately addressed the challenge of reducing chip size while maintaining effective power delivery and pixel functionality.
Innovation Solution
The development of an image sensor with an organic photoelectric layer, featuring a semiconductor substrate with active and black pixel regions, transparent electrode layers, and an interconnection layer that connects pads to the upper transparent electrode layer, allowing for reduced chip size and efficient power delivery without the need for additional power circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional power circuit region is used to deliver power to transparent electrode layers, then power delivery is achieved, but the chip size increases
Solution Approach 1:
The patent transitions power delivery from a planar circuit region approach to a vertical stacked approach. The interconnection layer is positioned at the same level as or higher than the pad surface, creating a three-dimensional power delivery architecture that eliminates the need for a dedicated power circuit region, thereby reducing chip area while maintaining reliable power delivery to the transparent electrode layers
Solution Approach 2:
The patent merges the power delivery function with the interconnection layer structure. The interconnection layer serves dual purposes: it provides mechanical support and electrical connection while simultaneously delivering power to the transparent electrode layers. This integration eliminates the need for separate power circuit regions, reducing overall chip size
2Reliability
If transparent electrode layers are extended across black pixel regions to deliver power, then power delivery is improved, but the sensor area increases
Solution Approach 1:
The patent segments the transparent electrode layers into functionally distinct regions: light-receiving areas over active pixels and power delivery areas over black pixel regions. The interconnection layer is strategically positioned to deliver power only to the necessary transparent electrode regions without extending across the entire sensor area, thus maintaining efficient power delivery while minimizing sensor area occupation
3Reliability
If additional power circuitry is added to ensure reliable power delivery, then power delivery reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the power delivery function from complex circuitry and implements it through a simplified interconnection layer structure. The interconnection layer directly connects pads to transparent electrode layers without requiring additional power management circuits, voltage regulators, or complex wiring, thereby achieving reliable power delivery with minimal device complexity
Solution Approach 2:
The interconnection layer serves multiple functions simultaneously: it provides mechanical support, establishes electrical connections, and delivers power to transparent electrode layers. This multi-functionality eliminates the need for dedicated power circuitry, reducing device complexity while ensuring reliable power delivery
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves miniaturization of image sensors by eliminating the need for a power circuit region, reducing the sensor's area, and ensuring reliable power delivery to the upper transparent electrode layer, thereby enhancing the image sensor's performance and reliability.
Implementation Method 1
Image sensors convert images into electric signals
Implementation Method 2
a plurality of first transparent electrode layers disposed over the semiconductor substrate and respectively corresponding to the plurality of active pixels; a second transparent electrode layer integrally formed across the plurality of active pixels
Implementation Method 3
an interconnection layer located at a level that is the same as or higher than an upper surface of the pad with respect to an upper main surface of the semiconductor substrate, the interconnection layer extending from the pad to the second transparent electrode layer, and comprising a connector electrically connecting the pad and the second transparent electrode layer
Data Source
AI summary
An image sensor of reduced chip size includes a semiconductor substrate having an active pixel region in which a plurality of active pixels are disposed and a power delivery region in which a pad is disposed. A plurality of first transparent electrode layers is disposed over the semiconductor substrate, respectively corresponding to the plurality of active pixels. A second transparent electrode layer is integrally formed across the active pixels. An organic photoelectric layer is disposed between the plurality of first transparent electrode layers and the second transparent electrode layer. An interconnection layer is located at a level that is the same as or higher than an upper surface of the pad with respect to an upper main surface of the semiconductor substrate. The interconnection layer extends from the pad to the second transparent electrode layer, and includes a connector electrically connecting the pad and the second transparent electrode layer.