Stacked Image Sensor Joint Portion Wire Resistance
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Solution Overview
Problem
The existing solid-state image pickup elements with stacked pixel and logic substrates face challenges in minimizing wire resistance and optimizing layout area due to stringent metal wire layer and narrow wiring spacing requirements, which affects chip size, manufacturability, and high-speed clock signal transmission.
Innovation Solution
The solution involves a joint portion where uppermost-layer wires of the pixel and logic substrates face each other, with specific terminal connections using first and second wires, and connection wires to reduce wire resistance and increase flexibility, allowing for a more efficient layout by utilizing empty spaces in the pixel substrate's wire layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If minimal wires are used to connect pixel substrate and logic substrate, then chip size is reduced, but wire resistance increases
Solution Approach 1:
The patent utilizes the vertical stacking dimension to reduce wire resistance. By connecting the pixel substrate and logic substrate through multiple wire layers in the vertical direction rather than using long horizontal wires, the effective wire length is reduced, thereby lowering resistance while maintaining compact chip footprint.
Solution Approach 2:
The patent introduces joint portions as intermediary connection structures between the pixel substrate and logic substrate. These joint portions provide multiple wire layers that act as intermediate connection paths, allowing signals to transfer between substrates with reduced resistance compared to direct minimal wire connections.
2Area of stationary object
If narrow wiring spacing is used, then layout area is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the wiring structure into multiple distinct wire layers within the joint portions. This segmentation allows each wire layer to be manufactured and positioned independently, reducing the cumulative precision requirements compared to creating narrow spacing in a single layer, while still achieving compact overall layout.
3Device complexity
If minimal wire connections are used between substrates, then chip complexity is reduced, but circuit operation reliability decreases
Solution Approach 1:
The patent merges multiple wire layers within the joint portions to create redundant connection paths between the pixel substrate and logic substrate. This merging provides multiple parallel pathways for signal transmission, ensuring that if one wire path fails, alternative paths can maintain circuit operation, thereby improving reliability without significantly increasing overall structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces wire resistance, enables wider power and ground wires, and facilitates higher-speed clock signal transmission, thereby optimizing the layout area and reducing chip size while maintaining effective circuit operations.
Implementation Method 1
a pixel array where a unit pixel including a photoelectric-conversion element is disposed in rows and columns
Data Source
AI summary
A solid-state image pickup element comprises a pixel substrate having a pixel array; a logic substrate having a logic circuit that relates to the pixel array, and stacked on the pixel substrate; and a joint portion joined in such a manner that uppermost-layer wires of the respective pixel substrate and logic substrate face each other, wherein the logic circuit has a first terminal and a second terminal that are nodes identical to each other, the node of the first terminal and the node of the second terminal are nodes that are used for a circuit operation on only the logic substrate, the joint portion includes a first wire connecting the first terminal to the pixel substrate, and a second wire connecting the second terminal to the pixel substrate, and the pixel substrate includes a first connection wire connecting the first wire and e second wire together.