CMOS Image Sensor Contact Structure for Low Dark Current
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Solution Overview
Problem
Conventional CMOS image sensors face challenges with high leakage current due to self-aligned silicide formation in the photosensitive areas, leading to increased dark current and reduced image quality, which is exacerbated by metal contamination from tungsten and metal silicide in contact holes, necessitating a non-silicide metal process that results in high contact resistance and poor device performance.
Innovation Solution
A semiconductor image sensor device is designed with a salicide block layer covering the MOS transistor in the image-sensing pixel region, using doped polysilicon plugs and conductive metal layers with no silicide layer on the source, drain, or gate, and a thin interlayer dielectric layer to reduce metal contamination and dark current, while maintaining low contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If self-aligned silicide process is used to improve RC delay, then device performance is improved, but leakage current increases and image quality deteriorates
Solution Approach 1:
The patent applies different treatments to different regions: silicide is formed only in the logic circuit region while the photoactive area remains free of silicide. This is achieved by using a sacrificial oxide layer that is selectively removed in the logic region, allowing silicide deposition only where needed. This resolves the contradiction by providing low RC delay in logic circuits while maintaining low leakage current in the photosensitive areas.
2Object-generated harmful factors
If non-silicide metal process is used to reduce dark current, then dark current is reduced, but contact resistance increases and device performance deteriorates
Solution Approach 1:
The patent uses non-silicide metal (such as tungsten or copper) specifically in the photoactive area where low dark current is critical, while allowing silicide-based contacts in the logic circuit region where low contact resistance is more important. This spatial differentiation resolves the contradiction by optimizing each region for its primary requirement.
Solution Approach 2:
The contact structure employs composite materials combining non-silicide metal with doped polysilicon in the photoactive area. This composite approach provides both low dark current (from the non-silicide metal) and adequate electrical contact (from the doped polysilicon), resolving the contradiction between dark current reduction and contact resistance maintenance.
3Speed
If silicide is formed in photodiode area and source/drain area, then RC delay is reduced, but metal contamination increases and image quality deteriorates
Solution Approach 1:
The patent employs a sacrificial oxide layer that is selectively present only in the logic circuit region, allowing silicide formation exclusively in that area. The photoactive area maintains its native oxide, preventing silicide formation and subsequent metal contamination. This resolves the contradiction by confining silicide benefits to logic circuits while protecting the photosensitive areas from contamination.
Solution Approach 2:
The native oxide layer in the photoactive area serves as an intermediary barrier that prevents metal contamination from reaching the photodiode. This thin oxide layer allows electrical functionality while blocking contaminant diffusion, resolving the contradiction between achieving low RC delay and preventing metal contamination.
Data Source
AI summary
An image sensor device includes a transistor disposed in a pixel region; a salicide block layer covering the pixel region; a first ILD layer covering the salicide block layer; a second ILD layer on the first ILD layer; a source contacts extending through the second and first ILD layers and the salicide block layer, and including first polysilicon plug in the first ILD layer and first conductive metal layer on the first polysilicon plug; and a drain contact extending through the second and first ILD layers and the salicide block, and including second polysilicon plug in the first ILD layer and second conductive metal layer on the second polysilicon plug.