Image Sensor Pixel Layout for Low Trap Density Channels
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Solution Overview
Problem
The increasing integration of image sensors has led to smaller pixel sizes, resulting in image quality degradation due to image transfer delays and component arrangement issues, which affect trap characteristics and noise performance.
Innovation Solution
The design of an image sensor with a substrate featuring a photoelectric conversion region, semiconductor patterns, and a gate electrode, where the semiconductor patterns include sub-patterns extending in different directions, improving trap characteristics and noise performance by utilizing surfaces with low interfacial trap densities as channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel size is reduced to increase integration degree, then productivity is improved, but image quality deteriorates due to image transfer delay and component arrangement issues
Solution Approach 1:
The semiconductor pattern is divided into multiple sub-patterns (first, second, and third sub-patterns) that extend in different directions. This segmentation allows for optimized charge transfer paths and reduced image transfer delay while maintaining compact pixel size, thereby improving image quality without sacrificing integration density.
Solution Approach 2:
The semiconductor sub-patterns extend in different directions (first direction, second direction, and third direction) rather than being confined to a single plane or linear arrangement. This multi-dimensional configuration optimizes the spatial arrangement of source/drain regions and gate electrodes, reducing charge transfer path length and improving image quality while maintaining small pixel size for high integration.
2Productivity
If pixel size is reduced, then integration degree is improved, but trap characteristics deteriorate
Solution Approach 1:
Different sub-patterns are configured with specific directional extensions to optimize local charge transfer characteristics. The first, second, and third sub-patterns extend in different directions to create optimized local electric field distributions that reduce charge trap phenomena at critical interfaces, thereby improving trap characteristics while maintaining reduced pixel size for high integration.
3Productivity
If pixel size is reduced, then integration degree is improved, but noise characteristics deteriorate
Solution Approach 1:
The semiconductor pattern is segmented into multiple sub-patterns extending in different directions, which optimizes the spatial separation of charge transfer paths. This segmentation reduces noise by minimizing interference between adjacent charge transfer regions while maintaining compact pixel dimensions for high integration degree.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the image sensor's trap characteristics and noise performance, leading to improved image quality by reducing charge trap phenomena and noise levels.
Implementation Method 1
a substrate including a photoelectric conversion region
Data Source
AI summary
An image sensor that includes a substrate including a photoelectric conversion region, a semiconductor pattern on the substrate, a gate electrode on the semiconductor pattern, and a gate insulating layer between the semiconductor pattern and the gate electrode. The semiconductor pattern includes a first sub pattern including a first source/drain region, a second sub pattern including a second source/drain region, and a third sub pattern between the first sub pattern and the second sub pattern. The gate electrode is on the third sub pattern. The first sub pattern, the second sub pattern, and the third sub pattern extend along different directions.