Image Sensor PD Oxide Layering for Lower Dark Current
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Solution Overview
Problem
Existing methods for manufacturing large-pixel CMOS image sensors result in surface etching damage and plasma interference during poly etch, leading to increased dark current and poor pixel area performance.
Innovation Solution
A method involving the formation of a supplemental oxide layer in the PD area before gate oxide layer formation, followed by blanket etching during DG-ET and poly etch, to reduce surface damage and plasma interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If blanket etching is performed on the device wafer during poly etch, then the etching process is simple and efficient, but surface etching damage and plasma interference occur in the PD area
Solution Approach 1:
The patent divides the device wafer surface into different regions (PD area and non-PD area) and applies different etching treatments to each region. A mask layer is formed to cover the non-PD area, allowing selective etching of the PD area while protecting other regions from plasma interference and surface damage.
Solution Approach 2:
The patent applies different protective measures to different areas of the device wafer. The mask layer is selectively formed only in the non-PD area, providing local protection where needed while allowing the PD area to undergo controlled etching. This creates local quality differentiation in the etching process.
2Reliability
If the oxide layer is made shallow to improve lag performance, then lag performance improves, but blocking during poly etch becomes insufficient
Solution Approach 1:
The patent performs preliminary protective action by forming a mask layer in the non-PD area before the poly etch process. This preliminary protection ensures that when blanket etching is performed, only the PD area is etched while the non-PD area is already protected, preventing plasma interference and surface damage.
3Reliability
If large-pixel sensors are manufactured with shallow N-type injection, then lag performance improves, but FWC relies heavily on shallow-layer injection requiring minimum etching damage
Solution Approach 1:
The patent segments the device wafer into PD area and non-PD area, applying selective etching protection to preserve surface integrity in the non-PD area while allowing necessary etching in the PD area. This segmentation approach maintains the shallow N-type injection benefits for lag performance while protecting against surface damage.
Solution Approach 2:
The patent applies local quality differentiation by forming a mask layer only in the non-PD area, providing enhanced protection where surface integrity is critical for FWC while allowing controlled etching in the PD area where lag performance optimization is the priority.
Data Source
AI summary
The present application discloses a method for making an image sensor, wherein an additional supplementary oxide layer is added in a PD area of a pixel cell before the formation of a gate oxide layer, a layer of a first photoresist is added and photoetching is used to define a PD area of a non-pixel cell, a supplementary oxide layer outside the PD area is removed by etching, retaining the supplementary oxide layer in the PD area. Thus, a relatively thick oxide layer can be formed in the PD area before polysilicon generation, blanket etching can be performed on the surface of the PD area during subsequent DG-ET (double-gate etching) and poly etch, and surface damage can be avoided during etching, reducing the plasma interference, and ultimately, the pixel dark current to improve pixel performance.