Image Sensor Transfer Line Forking for RC Delay Artifact Reduction
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Solution Overview
Problem
High pixel count image sensors experience significant resistance-capacitance (R-C) delay along row select lines, leading to exposure and read timing differences between columns, causing noticeable artifacts in images.
Innovation Solution
The implementation of an image sensor array with phase detection rows, normal multiple-photodiode cells, and compensation rows, where photodiode transfer lines are forked into sublines and driven by decoders at both ends, and selection transistors are distributed among the sublines to reduce R-C delay, along with the use of dummy photodiode cells to balance capacitive loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If high pixel count image sensors use traditional row select line configuration, then photodiode array coverage is improved, but resistance-capacitance delay increases causing image artifacts
Solution Approach 1:
The patent divides the traditional single row select line into multiple segmented line groups (first, second, third, and fourth line groups) that are distributed across different regions of the photodiode array. Each line group serves a specific column region, reducing the length and capacitive load of individual lines. This segmentation allows the photodiode array to maintain large coverage area while each segmented line experiences reduced RC delay, preventing image artifacts.
2Length of stationary object
If photodiode transfer lines are extended to cover more columns, then array width is improved, but propagation delay increases causing timing differences between columns
Solution Approach 1:
The patent segments the photodiode transfer lines into multiple shorter lines grouped in sets (first through fourth line groups), where each line in a group serves adjacent columns. This segmentation reduces the propagation delay for each individual line while collectively covering the full array width. The grouped structure ensures that columns served by the same line group experience matched timing, eliminating horizontal artifacts.
Solution Approach 2:
The patent organizes transfer lines into a two-dimensional grouping structure where lines are arranged in groups that serve specific column regions. This dimensional organization allows the system to manage long-distance signal distribution by creating a hierarchical structure: individual lines serve local column groups, while the grouping pattern covers the entire array width. This approach reduces propagation delay by limiting individual line lengths while maintaining comprehensive coverage.
Data Source
AI summary
In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.