Backside Illuminated Image Sensor Solid Conducting Layer
Solution Overview
Problem
The existing Chip Scale Packaging (CSP) processes for backside illuminated image sensors face challenges with low yield due to dielectric erosion and metal dishing effects during chemical-mechanical polishing, leading to increased electrical resistance and wasted wafer space from notched slotted metal layers.
Innovation Solution
The implementation of a wafer level processing technique using a solid conducting layer (TME layer) and through silicon via (TSV) to maximize wafer area and improve electrical I/O characteristics, eliminating the need for side-mounted connectors and minimizing CMP-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical-mechanical polishing (CMP) is used to planarize the substrate, then the substrate surface is flattened, but dielectric erosion and metal dishing effects occur leading to increased electrical resistance and low yield
Solution Approach 1:
The patent extracts and removes the problematic notched slotted metal layer structure from the design. Instead of using metal layers with notches and slots that require CMP processing, the invention uses a solid conducting layer that eliminates the need for such aggressive planarization, thereby preventing dielectric erosion and metal dishing effects while maintaining electrical connectivity
Solution Approach 2:
The patent inverts the conventional approach by placing the conducting layer on the backside of the substrate rather than on the front side with notched slotted structures. This backside illumination approach with solid conducting layer eliminates the CMP-related defects while achieving the desired electrical and optical performance
2Ease of operation
If notched slotted metal layers are used for I/O pads, then side-mounted connectors can be accommodated, but wafer space is wasted and manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional front-side pad structure by implementing solid pad portions on the backside of the substrate. This allows I/O connectivity without requiring notched slotted metal layers, thereby maximizing wafer space utilization while maintaining ease of operation for connector integration
Solution Approach 2:
The patent moves the I/O pad structure from the front side (2D plane) to the backside (third dimension), allowing solid pad portions to provide electrical connectivity without the need for lateral notches and slots. This dimensional change eliminates space waste while maintaining connector compatibility
3Ease of operation
If through holes are included in conducting layers, then I/O terminals can be formed, but wafer area is reduced and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the through holes from the conducting layer structure. Instead of creating holes through the conducting layer to form I/O terminals, the invention uses solid pad portions that provide direct electrical connectivity, thereby maximizing wafer area while maintaining ease of operation for terminal formation
Solution Approach 2:
The patent inverts the approach by using solid conducting material rather than removing material to create through holes. The solid pad portions on the backside provide I/O terminals without requiring holes, thus preserving wafer area while enabling terminal formation
Data Source
AI summary
An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.