Low-Profile Image Sensor Package with Trench Substrate
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Solution Overview
Problem
Current packaging methods for image sensors, such as chip-on-board and shellcase wafer level CSP, face challenges with assembly limitations, size constraints, yield issues, and limited I/O connections, making them difficult and costly for high-pixel image sensors, especially in achieving low-profile and reliable mechanical support and electrical connectivity.
Innovation Solution
A low-profile image sensor package is formed using a substrate with photo detectors and contact pads, where a second substrate is mounted with trenches and conductive traces exposed, allowing for dicing into separate assemblies that are then mounted on a printed circuit board with a cavity and conductive connections, providing mechanical support and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chip-on-board or shellcase wafer level CSP packaging methods are used for high-pixel image sensors, then assembly and manufacturing can be performed using existing processes, but assembly becomes increasingly difficult, yield problems occur, and capital investment requirements increase
Solution Approach 1:
The packaging process is segmented into distinct stages: wafer-level preparation (forming trenches, openings, and conductive traces on the support substrate before mounting image sensors), followed by post-dicing assembly (mounting individual diced image sensor assemblies to the PCB). This segmentation allows each stage to be optimized independently, improving both assembly ease and yield.
Solution Approach 2:
Complex preparatory actions are performed in advance at the wafer level, including forming trenches into the support substrate, creating openings, depositing conductive traces, and mounting the image sensor wafer to the support substrate before dicing. This preliminary action simplifies the final assembly step and improves yield by resolving complexity earlier in the process.
2Productivity
If standard WLP packages with chip area equal to package area are used, then packaging density is maximized, but the number of I/O connections is limited
Solution Approach 1:
The invention utilizes the vertical dimension by forming trenches and openings that extend through the support substrate thickness. This allows conductive traces to be routed in three-dimensional space rather than being constrained to a single plane, enabling increased I/O connections without increasing the horizontal package footprint.
Solution Approach 2:
The image sensor assembly is nested within a cavity formed in the PCB, allowing the image sensor substrate to be positioned in a recessed area. This nesting approach maximizes space utilization and enables additional I/O connections while maintaining a compact overall package size.
3Reliability
If longer interconnect lengths are used in existing packaging methods, then mechanical support and electrical connectivity can be achieved, but electrical performance deteriorates and chip power consumption increases
Solution Approach 1:
The invention extracts and eliminates unnecessary intermediate interconnect structures by establishing direct electrical connections between the image sensor contact pads and the PCB through conductive traces formed in the support substrate. This removal of redundant interconnect layers shortens the electrical path, reducing power consumption and improving electrical performance while maintaining mechanical support.
4Volume of moving object
If low-profile packaging is achieved through existing methods, then space limitations are addressed, but assembly limitations and size constraints prevent effective implementation
Solution Approach 1:
All complex structural preparations including trench formation, opening creation, and conductive trace deposition are completed in advance at the wafer level before dicing and final assembly. This preliminary action enables low-profile packaging to be achieved without compromising assembly feasibility, as the individual assembly steps become simpler and more manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a cost-effective and reliable low-profile packaging solution that improves electrical performance and reduces chip power consumption by allowing for shorter interconnect lengths and increased I/O connections, addressing the limitations of existing methods.
Implementation Method 1
image sensors, which are IC devices that include photo-detectors which transform incident light into electrical signals
Data Source
AI summary
An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors.