3D Stacked Image Sensor Readout Layout for Faster Signal Settling
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Solution Overview
Problem
Conventional CMOS image sensors suffer from high RC delay and slow readout speed due to long conductive paths and TSVs, which result in increased RC delay and decreased chip speed.
Innovation Solution
A high-speed readout image sensor design that includes a first chip with photodetector cells and transistor cells, a second chip with transistor cells and through-substrate vias (TSVs) vertically coupled to a readout circuit, and a third chip with readout circuits, where the readout circuits are laterally positioned between TSVs, reducing overall conductive path lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional CMOS image sensor design with long conductive paths and TSVs is used, then device functionality is achieved, but RC delay increases and readout speed decreases
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture, positioning readout circuits vertically adjacent to photodetector cells across different substrate layers. This dimensional change dramatically shortens conductive paths by eliminating long lateral interconnects and reducing TSV traversal distances, directly reducing RC delay and increasing readout speed
Solution Approach 2:
The image sensor is segmented into multiple functional chips (photodetector chip, readout circuit chip, etc.) that are vertically stacked and bonded together. Each chip handles specific functions, allowing optimized local interconnections within chips and reduced overall signal path lengths through the stack, resolving the RC delay issue while maintaining full functionality
2Productivity
If long conductive paths are used to connect photodetectors to readout circuits, then complete electrical connectivity is achieved, but chip speed decreases due to increased RC delay
Solution Approach 1:
The patent employs vertical stacking to transform long lateral conductive paths into short vertical interconnections through TSVs. Readout circuits are positioned directly above or below photodetector cells in adjacent substrate layers, reducing conductive path length from millimeter-scale lateral routes to micrometer-scale vertical links, thereby increasing chip speed
Solution Approach 2:
Multiple functional layers are nested vertically, with each substrate layer containing specific circuit elements positioned directly over underlying layers. This nested arrangement ensures that signal paths traverse minimal distances between functional blocks, reducing RC delay and enhancing chip speed while maintaining complete electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a fast readout speed with reduced RC delay and increased chip speed by minimizing conductive path lengths, resulting in quicker signal settling times.
Implementation Method 1
The image sensors comprise one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output electrical signals corresponding to the incident radiation
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.