Image Sensor Vertical Transmission Gate Pixel Miniaturization
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Solution Overview
Problem
Time-of-flight (ToF)-based image sensors face challenges in miniaturizing pixels due to the difficulty in reducing the area occupied by multiple gates, which hinders the miniaturization of image sensors and increases read noise.
Innovation Solution
The image sensor design includes vertically extended transmission gates and large storage gates, allowing for a miniaturized pixel structure with increased charge storage capacity and reduced read noise by optimizing the arrangement of gates and charge storage regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple gates are arranged horizontally in conventional image sensors, then charge storage capacity can be maintained, but pixel area increases and miniaturization is hindered
Solution Approach 1:
The patent transitions from horizontal arrangement of gates to vertical arrangement, utilizing the thickness direction (Z-axis) of the semiconductor substrate. Multiple gates (first gate, second gate, third gate) are stacked vertically through the well region, converting a 2D planar layout into a 3D vertical structure. This dimensional change allows charge storage capacity to be maintained while significantly reducing the horizontal pixel area.
Solution Approach 2:
The patent implements a nested structure where gates are embedded within the well region in a hierarchical arrangement. The first gate, second gate, and third gate are positioned at different vertical levels within the same horizontal footprint, creating a nested configuration that maximizes space utilization and enables miniaturization while preserving charge storage capacity.
2Area of moving object
If pixel size is reduced for miniaturization, then device complexity decreases, but read noise increases
Solution Approach 1:
By arranging gates vertically through the well region rather than horizontally, the patent creates sufficient charge storage volume within a reduced horizontal footprint. This vertical stacking allows the pixel area to be minimized while the charge storage capacity along the vertical dimension compensates for the reduced area, thereby maintaining signal-to-noise ratio and reducing read noise.
Solution Approach 2:
The patent changes the spatial distribution parameter of charge storage from horizontal expansion to vertical accumulation. By modifying the geometric configuration of gates and charge storage regions along the thickness direction, the patent achieves miniaturization while maintaining adequate charge storage volume to minimize read noise through improved charge collection efficiency.
Data Source
AI summary
An image sensor includes a semiconductor substrate including a first surface and a second surface and further includes a well region and a first floating diffusion region that are each adjacent to the first surface. The image sensor includes a first vertical transmission gate and a second vertical transmission gate isolated from direct contact with each other and each extend from the first surface of the semiconductor substrate and in a thickness direction of the semiconductor substrate through at least a portion of the well region. The image sensor includes a first storage gate between the first vertical transmission gate and the first floating diffusion region and on the first surface of the semiconductor substrate. The image sensor includes a first tap transmission gate between the first storage gate and the first floating diffusion region and on the first surface of the semiconductor substrate.