Image Sensor Via Layout Around Capacitors for Global Shutter

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Solution Overview

Problem

Highly integrated image sensors face challenges in securing space for vias around capacitors due to the space occupied by the capacitors, making it difficult to efficiently arrange vias in existing image sensor designs.

Innovation Solution

The image sensor incorporates both edge vias and central vias efficiently arranged around the capacitors, with edge vias along the edges and central vias interposed between the capacitors, allowing for improved integration and space utilization without altering the shape of the electrode pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If capacitors are placed in the wiring structure of highly integrated image sensors, then the image sensor can perform global shutter operation, but the space occupied by capacitors makes it difficult to secure space for vias around them

Engineering Contradiction:
Improveglobal shutter operation capabilityVSAvoidspace for via arrangement
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent introduces a vertical dimension for via placement by positioning vias at different heights relative to the capacitor structure. Specifically, vias are placed both above and below the capacitor electrodes in the vertical stacking direction, effectively utilizing the third dimension (Z-axis) to resolve the lateral space constraint. This allows multiple vias to be arranged around each capacitor without increasing the planar footprint, thereby enabling global shutter operation while maintaining sufficient via spacing for reliable connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If more vias are arranged around capacitors to improve connection, then the integration and performance of image sensor are enhanced, but the space required for via placement becomes insufficient due to capacitor occupation

Engineering Contradiction:
Improveconnection reliabilityVSAvoidavailable space for via placement
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements a nested arrangement where vias are positioned in the vertical spaces above and below capacitor electrodes, effectively nesting the via structures within the vertical envelope of the capacitor. This nesting approach allows multiple connection points to be established around each capacitor without requiring additional lateral space, thereby improving connection reliability while accommodating the limited planar area available in highly integrated image sensors.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This arrangement enables efficient placement of vias around the capacitors, enhancing the integration and performance of the image sensor while maintaining the existing electrode pad configurations.

Implementation Method 1

a photoelectric conversion layer in the substrate

Methodology Applied
Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS11855115B2Image sensor
Publication Date: 2023.12.26 SAMSUNG ELECTRONICS CO LTD
  • US11855115B2 patent drawing
  • US11855115B2 patent drawing
  • US11855115B2 patent drawing

AI summary

An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.