CMOS Image Sensor Well Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The interconnect layers in CMOS image sensors introduce parasitic capacitance that negatively affect the performance of pixel sensors by increasing RC delay, leading to reduced responsiveness, degraded imaging performance, and increased power consumption.
Innovation Solution
Incorporating a doped well region in the substrate layer adjacent to elongated conductive structures to introduce series capacitance, which reduces overall parasitic capacitance and lowers RC delay, thereby enhancing sensor responsiveness and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnect layers are used to connect pixel sensors, then electrical connectivity is achieved, but parasitic capacitance increases causing degraded imaging performance
Solution Approach 1:
The patent introduces a doped well region that generates series capacitance to counteract the harmful parasitic capacitance from interconnect layers. By converting the harmful capacitive effect into a beneficial series capacitance configuration, the overall RC delay is reduced, improving imaging performance while maintaining necessary electrical connectivity through interconnect layers
2Reliability
If interconnect layers are used to connect pixel sensors, then electrical connectivity is achieved, but RC delay increases reducing responsiveness
Solution Approach 1:
The doped well region creates series capacitance that transforms the harmful parallel parasitic capacitance effect into a beneficial series configuration. This conversion reduces the overall RC time constant, thereby decreasing the time loss and improving sensor responsiveness while maintaining interconnect layer connectivity
3Reliability
If interconnect layers are used to connect pixel sensors, then electrical connectivity is achieved, but power consumption increases
Solution Approach 1:
By introducing the doped well region that generates series capacitance, the patent converts the harmful effect of parasitic capacitance into a beneficial configuration. This reduces the overall power consumption associated with charging and discharging parasitic capacitance during pixel sensor operation, while maintaining necessary electrical connectivity through interconnect layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced parasitic capacitance improves high-speed imaging and low-light performance, increases dynamic range, and decreases power consumption of the image sensor device.
Implementation Method 1
Incorporating a doped well region in the substrate layer adjacent to elongated conductive structures to introduce series capacitance, which reduces overall parasitic capacitance and lowers RC delay
Implementation Method 2
A pixel sensor of the CMOS image sensor may include a photodiode configured to convert photons of incident light to a photocurrent of electrons
Data Source
AI summary
A semiconductor die of an image sensor device includes a doped well region in a substrate layer of the semiconductor die. The doped well region may be included adjacent to an elongated conductive structure that extends vertically through the substrate layer into interconnect layers on opposing sides of the substrate layer. The doped well region introduces additional series capacitance between the elongated conductive structure and the substrate layer (which may be formed of one or more semiconductor materials). This additional series capacitance, which is electrically connected in series with parasitic capacitance associated with the elongated conductive structure, effectively reduces the overall parasitic capacitance in the control circuitry of the pixel sensors of the image sensor device.