Imager Pixel Layout Routing Common Signals

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional layouts for integrating imaging pixels face a challenge where the increasing number of signal lines competes with metal-insulator-metal (MiM) capacitors for metal layer allocation, reducing the dynamic range performance due to reduced area allocation for capacitors.

Innovation Solution

The proposed layout includes a signal line traversing certain imaging pixels and metal interconnects that transmit signals to adjacent pixels, organized in a mirrored pattern, allowing for reduced metal interconnect length and allocation of more metal layers to MiM capacitors, thereby increasing well capacity and dynamic range performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple signal lines are used to transmit common signals to adjacent imaging pixels, then signal transmission coverage is improved, but the area available for MiM capacitors is reduced

Engineering Contradiction:
Improvesignal transmission coverageVSAvoidarea for MiM capacitors
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent introduces a third metal layer to resolve the conflict between signal lines and MiM capacitors. Signal lines are routed on the third metal layer while MiM capacitors are formed on first and second metal layers, allowing both functions to coexist without area conflict. This dimensional separation enables full signal transmission coverage while preserving maximum capacitor area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the metal layer functions by allocating different layers for different purposes: first and second metal layers for MiM capacitors, and third metal layer for signal lines. This segmentation eliminates competition for space and allows each component to occupy its designated layer fully.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If the area of metal layers allocated to MiM capacitors is reduced, then more area is available for signal lines, but the well capacity and dynamic range performance are reduced

Engineering Contradiction:
Improvearea for signal linesVSAvoiddynamic range performance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

By moving signal lines to the third metal layer, the patent eliminates the need to reduce MiM capacitor area on lower layers. The vertical stacking of functions across multiple layers allows signal lines to have sufficient area and routing flexibility without compromising capacitor size, thereby maintaining well capacity and dynamic range performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The segmentation of metal layer functions ensures that MiM capacitors on first and second layers maintain their required area for optimal performance, while signal lines on the third layer obtain sufficient space for routing. This functional segmentation prevents the trade-off between signal line area and capacitor area.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If signal lines traverse through imaging pixels, then signal distribution is simplified, but metal interconnect length increases

Engineering Contradiction:
Improvesignal distribution complexityVSAvoidmetal interconnect length
Core Design Contradiction:
Device complexityVSLength of stationary object

Solution Approach 1:

The patent uses the third metal layer for signal line routing, which provides a dedicated plane for signal distribution that does not interfere with pixel internal structures. This allows signal lines to traverse pixels with optimized routing paths, reducing the required interconnect length compared to routing on lower layers that must navigate around capacitor structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9496299B1Layout for routing common signals to integrating imaging pixels
Publication Date: 2016.11.15 SENSORS UNLIMITED INC
  • US9496299B1 patent drawing
  • US9496299B1 patent drawing
  • US9496299B1 patent drawing

AI summary

An imager is provided that includes an integrated circuit. The integrated circuit includes at least one metal layer, a signal line extending in a first direction, and a pixel cell. The pixel cell includes imaging pixels and a metal interconnect. The imaging pixels include first, second, third, and fourth imaging pixels, arranged in two rows and two columns, each imaging pixel having a metal-insulator-metal (MiM) capacitor disposed on the at least one metal layer, the first and second imaging pixels being traversed by the signal line to receive signals from the signal line. The metal interconnect extends in a second direction different than the first direction and is coupled to the signal line and the third imaging pixel to transmit the signals to the third imaging pixel. The third imaging pixel is adjacent to the first imaging pixel and is disposed in a different column or row than the second imaging pixel.