Solid-State Imaging Device Charge Accumulation Layer Design

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Solution Overview

Problem

Solid-state imaging devices with global electronic shutter function face challenges in improving sensitivity and charge accumulation while minimizing noise from signal carrier leakage into holding portions.

Innovation Solution

The design incorporates a p-type semiconductor region under the n-type semiconductor region forming a charge accumulation layer, with a p-n junction capacitor structure and strategically placed openings to enhance charge accumulation and reduce noise by collecting electrons in the n-type semiconductor region, thereby increasing sensitivity and preventing leakage into holding portions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a p-type semiconductor region is provided under the n-type semiconductor region forming a charge accumulation region, then the charge accumulation amount of the photoelectric conversion unit is increased, but signal carriers may leak from the photoelectric conversion unit into the holding portion

Engineering Contradiction:
Improvecharge accumulation amountVSAvoidsignal carrier leakage
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

A first n-type semiconductor region is introduced as an intermediary between the photoelectric conversion unit and the holding portion. This intermediate region acts as a barrier to prevent signal carriers from leaking into the holding portion while allowing the p-type semiconductor region to maintain its charge accumulation function. The intermediary region effectively decouples the conflicting requirements of charge accumulation and leakage prevention.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The n-type semiconductor structure is segmented into multiple regions: the original n-type semiconductor region forming the photoelectric conversion unit, a first n-type semiconductor region (intermediary barrier), and an n-type semiconductor region forming the holding portion. This segmentation allows each region to perform its specific function independently, with the first n-type region serving as a protective barrier against signal carrier leakage.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the p-n junction capacitance is increased to improve sensitivity, then the charge accumulation amount increases, but the device complexity increases

Engineering Contradiction:
ImprovesensitivityVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The invention merges multiple functions into the p-n junction capacitor structure: charge accumulation, sensitivity enhancement, and leakage prevention. By integrating the first n-type semiconductor region into the existing p-n junction capacitor architecture, the design achieves leakage suppression without requiring completely separate structures, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The p-n junction capacitor structure is designed to perform multiple functions simultaneously: it serves as both the charge accumulation region and the leakage prevention barrier through the first n-type semiconductor region. This multi-functionality reduces the need for additional separate components, thereby managing device complexity while achieving multiple performance goals.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the sensitivity of the photoelectric conversion unit and reduces noise by effectively accumulating charges and preventing unwanted signal leakage, improving the overall performance of the imaging device.

Implementation Method 1

a photoelectric conversion unit that generates signal carriers

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Implementation Method 2

a p-type semiconductor region having a higher concentration than a well is arranged under an n-type semiconductor region forming a charge accumulation region to increase the p-n junction capacitance

Methodology Applied
Scientific Effectp-n junction capacitance: Capacitance

Implementation Method 3

a p-type semiconductor region having a higher concentration than a well is arranged under an n-type semiconductor region forming a charge accumulation region to increase the p-n junction capacitance

Methodology Applied
Scientific EffectImpurity concentration effect:

Implementation Method 4

an opening is provided in the p-type semiconductor region in order to prevent a reduction in the sensitivity due to the p-type semiconductor region being provided under the n-type semiconductor region as a charge accumulation region

Methodology Applied
Scientific EffectLight transmission:

Data Source

PatentEP3379575B1Solid-state imaging device, imaging system, and movable object
Publication Date: 2021.05.12 CANON KK
  • EP3379575B1 patent drawingFigure 1
  • EP3379575B1 patent drawingFigure 2
  • EP3379575B1 patent drawingFigure 3

AI summary

A solid-state imaging device includes a plurality of pixels each including a photoelectric conversion unit (D), a first holding portion (C1) holding charges transferred from the photoelectric conversion unit, a second holding portion (C2) holding charges transferred from the first holding portion, and an amplifier unit outputting a signal based on charges in the second holding portion. The photoelectric conversion unit includes a first conductivity type first semiconductor region, a second conductivity type second semiconductor region thereunder, a first conductivity type third semiconductor region thereunder, and a second conductivity type fourth semiconductor region thereunder. The first holding portion includes a second conductivity type fifth semiconductor region and a first conductivity type sixth semiconductor region thereunder at a depth of the third semiconductor region being provided. A semiconductor region having a lower potential than the third semiconductor region and the sixth semiconductor region is provided between the third and sixth semiconductor regions.