Solid-State Imaging Device Wire Layout for Shading Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional solid-state imaging devices experience irregularities in image brightness due to varying light incidence and capacitance changes, leading to shading issues, particularly in applications requiring high image quality.
Innovation Solution
The design of the solid-state imaging device includes a pixel array with a specific wire layout where the vertical signal line is shifted towards the center line of the pixel array, and contacts are positioned to equalize light incidence from different directions, reducing capacitance variations and preventing mixed colors by using different wiring layers for the effective and light-shielded pixel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If wires are arranged in conventional layouts with different lateral shapes, then manufacturing is simplified, but light incidence varies causing irregular brightness (shading)
Solution Approach 1:
The patent applies local quality by making the wire shapes position-dependent. Wires at different lateral positions have different shapes specifically designed to compensate for their location. This ensures that despite varying positions in the pixel array, all wires present equal optical resistance to oblique incident light, thereby achieving uniform brightness without requiring complex global redesign
Solution Approach 2:
The patent employs asymmetry by intentionally designing wires with different shapes at different lateral positions. Rather than using symmetric uniform wire layouts, the invention creates asymmetric wire configurations where each wire's shape is optimized for its specific position, preventing shading while maintaining manufacturing feasibility
2Manufacturing precision
If wiring layers are not separated for different pixel regions, then device complexity is reduced, but oblique incident light characteristics deteriorate causing mixed colors
Solution Approach 1:
The patent applies segmentation by dividing the pixel array into effective pixel regions and light-shielded pixel regions, each with dedicated wiring layers. This segmentation allows independent optimization of wire shapes and arrangements for each region type, ensuring that oblique incident light characteristics are specifically tailored to prevent color mixing in effective pixels while maintaining structural organization
Solution Approach 2:
The patent resolves the contradiction by transitioning to a multi-layer wiring structure (adding the vertical dimension). By stacking wiring layers at different heights, the invention can provide different wire configurations for effective and light-shielded regions without increasing lateral complexity, thus achieving color accuracy through vertical stratification
3Manufacturing precision
If capacitance variations are not compensated, then device complexity is low, but image brightness shows irregularities due to varying light incidence
Solution Approach 1:
The patent applies parameter changes by systematically varying wire shape parameters (width, length, position) based on lateral position. This parameter optimization compensates for capacitance variations caused by different light incidence angles at various positions, achieving brightness uniformity through precise geometric control rather than additional compensating circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses shading and improves oblique incident light characteristics, ensuring uniform light incidence and high-quality image output.
Implementation Method 1
a photodiode 2501 which accumulates an amount of electric charges corresponding to the intensity of received light
Data Source
AI summary
A pixel array is provided in which cells are arranged in a matrix. Each cell includes a photodiode, an FD, a transfer transistor, a reset transistor, an amplifying transistor having a gate electrode connected to the FD, a drain connected to a power supply line, and a source connected to a vertical signal line, and an FD wire. The FD wire is provided in a first wiring line, and the vertical signal line is provided in a second wiring line positioned over the first wiring layer. Since the potential of the FD wire follows the potential of the vertical signal line, it is possible to suppress a variation in capacitance occurring in the FD when a position of the vertical signal is shifted, depending on a position of the cell.