Stacked Solid-State Imaging Element With Vertical Multi-Gate Pixel Transistors

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. By stacking the first substrate containing photoelectric conversion elements with the second substrate containing pixel transistors vertically, the wiring connections are established through vertical vias rather than horizontal traces. This dimensional change reduces wiring length significantly while providing sufficient space for pixel transistors on the second substrate, thereby resolving the contradiction between securing transistor space and minimizing wiring length.

By implementing a vertical stacked architecture, the patent minimizes the wiring path length between photoelectric conversion elements and pixel transistors. The vertical via connections reduce parasitic resistance and capacitance compared to lateral wiring, thereby reducing energy loss and maintaining high photoelectric conversion efficiency while still providing adequate space for transistor operations on the separated second substrate.

The patent employs a multi-gate transistor structure on the second substrate where the gate electrode extends in multiple directions (e.g., U-shaped or T-shaped gate) to control the channel from multiple angles. This multi-gate configuration enables effective transistor control with compact footprint, achieving short wiring length connections to the first substrate while maintaining manageable device complexity through optimized gate geometry rather than excessive structural complexity.